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Visitor
Visitor
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Registered: ‎10-30-2019

XDMA PCIE IP,problem about AXI (out of order?) of the bypass interfence.

Hi, I used the bypass AXI interfence of the XDMA PCIE IP, with the Xilinx's Driver and software(.exe). (detail in Xilinx Answer 65444) I press the cmd below on the host PC: xdma_rw.exe bypass write 0x000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I try to receive the datas from the bypass AXI interfence in the FPGA, BUT I got the wrong data at the corresponding address. for example, at offset addr 0x008, I got 24 23 22 21 20 19 18 17.(but it should be 16 15 14 13 12 11 10 09) It's a problem called outstanding or out of order? How can I get the data in order according to the address? can I set the XDMA PCIE IP or change the Driver to solve this problem? Thank you very much
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Moderator
Moderator
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Registered: ‎02-16-2010

Hi @johnwell 

What do you read from address 0x000, 0x004?

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Visitor
Visitor
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Registered: ‎10-30-2019

Hi,

Thank you for your reply.

I make mistake in writing the AXI module, I have found the problem.

 

Best regard

johnwell