I use the GUI to generate my XDMA core for Artix 7. The default completion timeout selected here is 50us to 50ms. I do not see any way to change it. I saw in another post, a tcl script command to change it. If I change the value to say 250ms, it complains that I am exceeding the range. If I change it to say 10ms, it doesn't do anything.
I add the tcl command as tcl_post to synthesis settings in Vivado.
The PCIe core's documentation itself calls for following ranges from PG054-
CFGDEVCONTROL2CPLTIMEOUTVAL[3:0] Output USERCLK Configuration Device Control 2, Completion Timeout Value, DEVICECTRL2[3:0]. This 4-bit output is the time range that the user logic should consider a Request pending Completion as a Completion Timeout. The integrated block takes no action based on this setting. • 0000b: 50 μs to 50 ms (default) • 0001b: 50 μs to 100 μs • 0010b: 1 ms to 10 ms • 0101b: 16 ms to 55 ms • 0110b: 65 ms to 210 ms • 1001b: 260 ms to 900 ms • 1010b: 1 s to 3.5 s • 1101b: 4 s to 13 s • 1110b: 17 s to 64 s