01-16-2021 11:09 AM - edited 01-17-2021 11:39 AM
I'm trying to use the XDMA Bridge IP as a root port to communicate with a gen 3, 4-lane NVME SSD. When the SSD is a Samsung 970 EVO 1TB (https://www.newegg.com/samsung-970-evo-1tb/p/N82E16820147691), I see that cfg_ltssm_state goes to 0x10 and that user_lnk_up = 1. When I swap to a Sabrent Rocket 1TB (https://www.newegg.com/sabrent-rocket-nvme-1tb/p/0D9-001Y-00012?item=9SIAME8ANV9541&source=region&nm_mc=knc-googlemkp-pc&cm_mmc=knc-googlemkp-pc-_-pla-sabrent-_-solid+state+disk-_-9SIAME8ANV9541&gclid=CjwKCAiAuoqABhAsEiwAdSkVVKmXMQeMX0njlctUHDZmW3j27...), I see that cfg_ltssm_state goes to 0x10 but user_lnk_up = 0.
I checked the Phy Status/Control register at 0x144 offset for both cases:
So it looks like the Sabrent is negotiating to gen1 (2.5 Gbit/s) versus the Samsung which negotiates to gen 3 (8.0 Gbit/s).
In the pdf at the bottom of the Xilinx Answer 73361 (https://www.xilinx.com/support/answers/73361.html), at the bottom of page 22, it mentions checking the Link Status 2 register (offset 0xa0) to see where the link training failed. The values for register 0xa0 are:
Bits [31:16] correspond to the link status 2 register, so for the Sabrent, Phase 1, 2, 3 are not successful.
I saw on pages 12-14 of the same pdf that you could try different parameters in the "GT Settings" tab of the XDMA IP. I had been using "Enable Auto RxEq = false", "Form factor driven insertion loss adjustment = Chip-to-chip", and "Link Partner TX Preset = 4".
I tried changing "Enable Auto RxEq = true" and "Form factor driven insertion loss adjustment = Add-in card", but see the same values for both register 0x144 and 0xa0 as before for both Samsung and Sabrent drives.
Does anyone have any suggestions for what to try next? Any ideas why one SSD would work and not the other? They are both gen3, 4-lane, NVME 1.3 compliant.
Thanks for any help!
P.S. I'm using Vivado 2020.2 on 64-bit Ubuntu.
01-18-2021 01:36 AM - edited 01-18-2021 01:45 AM
Hi @henzer ,
if you haven't already do that, I suggest you to check the following projects/IPs from Xilinx:
Probably they can be helpful as references for your project and to solve your problem.