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Visitor linkquest18
Visitor
459 Views
Registered: ‎12-31-2018

XDMA constraints

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Hi, 

We are new to XDMA.

And we are trying to implement the XDMA (connected to DDR4) on a third-party development board.

We are folllowing PG195 and the Xilinx video tutorial ( https://www.xilinx.com/video/technology/dma-for-pci-express.html

In block design, is "xdma_0_0_peic3_ip_PCIE_X0Y0.xdc" (under the xdma ip folder) the constraint file needed? 

Do we need to modify it and manually add it to the design.

 

Thanks.

 

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1 Solution

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Moderator
Moderator
425 Views
Registered: ‎02-16-2010

Re: XDMA constraints

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Hi @linkquest18 ,

If xdma_0_0_peic3_ip_PCIE_X0Y0.xdc file is generated inside the IP, then it is a required file. In block design, tool picks this file automatically.

When targeting to third party board, you will have to ensure to

1. Select the correct PCIe hardblock location and GT quad in the GUI. 

2. Set the reset and refclk location in the top level .xdc based on the board schematics.

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2 Replies
Moderator
Moderator
426 Views
Registered: ‎02-16-2010

Re: XDMA constraints

Jump to solution

Hi @linkquest18 ,

If xdma_0_0_peic3_ip_PCIE_X0Y0.xdc file is generated inside the IP, then it is a required file. In block design, tool picks this file automatically.

When targeting to third party board, you will have to ensure to

1. Select the correct PCIe hardblock location and GT quad in the GUI. 

2. Set the reset and refclk location in the top level .xdc based on the board schematics.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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Visitor linkquest18
Visitor
404 Views
Registered: ‎12-31-2018

Re: XDMA constraints

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That clarify it. Thanks.

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