XDMA core error when run block automation

[yachli]

As a newbie, in vivado 2017.4, followed the video from https://www.xilinx.com/video/technology/dma-for-pci-express.html but a different device xc7z035ffg900-1, created a block design and add xdma ip core , then run block automation, it report error below

• apply_bd_automation -rule xilinx.com:bd_rule:xdma -config {auto_level "IP Level" lane_width "X1" link_speed "2.5 GT/s (PCIe Gen 1)" axi_clk "Maximum Data Width" axi_intf "AXI Memory Mapped" bar_size "1 (Megabytes)" bypass_size "Disable" h2c "2" c2h "2" } [get_bd_cells xdma_0]
• [BD 41-1273] Error running apply_rule TCL procedure: unbalanced open paren validate_link_lane Line 43 

any suggestion or an xdma example project on zynq to compatible driver from AR65444? thanks

[coryb]

Hello @yachli,

Does the same error occur when doing subsystem level automation? Looks like you are currently using IP Level automation.

Thanks,

Cory

[yachli]

Thanks @coryb, you are right. that's using IP Level automation, tried subsystem level automation seems ok.

Now the device show correctly in windows 10 device manager with driver from AR65444.

My first target is to run AR65444 well and final target is to let win10 , the PL  and the PS communicate(DMA) with each other.

Can you guys help to review the diagram and address? xdma_test.exe failed and report "Failed to read stream! 1359"

[venkata · Accepted solution]

Can you probe M_AXI interface of XDMA during the failure? You can use system ILA IP (https://www.xilinx.com/support/documentation/ip_documentation/system_ila/v1_0/pg261-system-ila.pdf) to do this. I find the interfaces mapped to M_AXI do not have any base address to be 0x0000_0000_0000_0000.

Can you try moving one of them to 0x0000_0000_0000_0000 and test?