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avinashc
Explorer
Explorer
370 Views
Registered: ‎10-09-2018

XDMA example design PaR error

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Hello,

system: artix 7 (xc7a50t-2csg325) , vivado 2020.2 , win10-64 bit

 

I have generated XDMA IP Core and using it's example design, but example design itself is giving error in PaR design.

 

 

[Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets xdma_0_support_i/xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out] >

	xdma_0_support_i/xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i (GTPE2_CHANNEL.TXOUTCLK) is locked to GTPE2_CHANNEL_X0Y3
	 xdma_0_support_i/pipe_clock_i/mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_gtpcommon_gtpchannel
	Status: PASS 
	Rule Description: A GTPCommon driving a GTPChannel must both be in the same clock region
	 xdma_0_support_i/gt_common_i_0/qpll_wrapper_i/gtp_common.gtpe2_common_i (GTPE2_COMMON.PLL0OUTCLK) is provisionally placed by clockplacer on GTPE2_COMMON_X0Y0
	 xdma_0_support_i/xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i (GTPE2_CHANNEL.PLL0CLK) is locked to GTPE2_CHANNEL_X0Y3

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	 xdma_0_support_i/pipe_clock_i/mmcm_i (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
	 xdma_0_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

	Clock Rule: rule_mmcm_mmcm
	Status: PASS 
	Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
	each other (vertically), if the  CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
	 xdma_0_support_i/pipe_clock_i/mmcm_i (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
	 xdma_0_support_i/pipe_clock_i/mmcm_i (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

	Clock Rule: rule_bufds_bufg
	Status: PASS 
	Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
	 refclk_ibuf (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
	 xdma_0_support_i/cpllpd_refclk_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

	Clock Rule: rule_bufds_gtp_common_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTPCommon must both be placed in the same or adjacent clock region
	(top/bottom)
	 refclk_ibuf (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
	 and xdma_0_support_i/gt_common_i_0/qpll_wrapper_i/gtp_common.gtpe2_common_i (GTPE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTPE2_COMMON_X0Y0

 

 

I have just added some missing constraint in .xdc file (about pin details).

 

1) why example design have error?

2) what can be done to check issue?

3) do I need to add this core with some other project to get going?

 

Thank You!

Avinash

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avinashc
Explorer
Explorer
240 Views
Registered: ‎10-09-2018

Hello @mmcnicho ,

problem solved.

Yes I am just using XDMA IP example design.

I had to introduce bufg in between txoutclk and mmcm input clk in "top/xdma_support_i/pipe_clk_i". that solved my issue. Input clk to bufg and output of bufg to clkin1 of mmcm.

But I did not understand why it was necessary.

 

Thank You!

View solution in original post

2 Replies
mmcnicho
Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎10-09-2019

Hi,

I will try reproducing the issue. I want to make sure I understand how to reproduce.

Are you simply using the XDMA IP example design?

Also, can you upload your .xci file. I will use this file to reproduce the issue.

Thanks

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avinashc
Explorer
Explorer
241 Views
Registered: ‎10-09-2018

Hello @mmcnicho ,

problem solved.

Yes I am just using XDMA IP example design.

I had to introduce bufg in between txoutclk and mmcm input clk in "top/xdma_support_i/pipe_clk_i". that solved my issue. Input clk to bufg and output of bufg to clkin1 of mmcm.

But I did not understand why it was necessary.

 

Thank You!

View solution in original post