I usual use vhdl as design language. I have 3 different xdma core (an example to test code by Xilinx with streaming interface, and xdma with streaming interface interfacing with the rest of my design and an xdma with memory map interfaceing with my design using DD# memory on our board.)
The issue I run into that when I set the language to verilog it will build and looks ok as in link is up but core will not show up with lspci so driver cannot be loaded. I upgraded from 2020.1 to 2020.2 and same issue. The reason why i have to use verilog design flow even that my top level file is VHDL is that I am using the DDR3 MIG with axi interface.
I might try to to use a method like in my old design flow using Mentor Precision to synthesize and use the memory controller's dcp as an ip block instead of the ip containers to get around using VHDl with the axi mig controller. Will need to port the timing constarins to my top level constraint file as never vivado versions do not support picking up timing constraints using a dcp.
Has any ran into this issue because it is really mind boggling... Will create a SR with Xilinx but want to ask on the forums