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Visitor
Visitor
1,017 Views
Registered: ‎03-31-2019

XDMA linux driver not showing devices?

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Hi,

I'm deveoping with the Xilinx's xdma linux driver. The problem I'm having is that everytime I load a new bitstream, the driver doesn't see any xdma devices in /dev.

I would have to reboot then do insmod xdma.ko then ls /dev would show the devices.

Is there any way I don't have to reboot the host after reloading bitstream?

 

Thanks for your help in advance!

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Xilinx Employee
Xilinx Employee
991 Views
Registered: ‎08-07-2007

hi @jssk 

 

please check this

 

https://www.xilinx.com/support/answers/37406.html

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
992 Views
Registered: ‎08-07-2007

hi @jssk 

 

please check this

 

https://www.xilinx.com/support/answers/37406.html

 

Thanks,

Boris

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Visitor
Visitor
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Registered: ‎03-31-2019

This is exactly what I needed, thank you!

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Visitor
Visitor
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Registered: ‎01-31-2019

Did that recommendation work? I ask because the original advice was from several years ago, and there are lots of different reports about some methods not working on some machines / linux versions etc..

The reason that you can't see the device after reconfiguring is that the PCIe core has lost connection with the PCIe root device on the motherboard.

Normally a motherboard boots, then queries all the attached devices, then configures the devices to operate at their maximum speed. This has to happen quite soon after power up, so the only way to get a PCIe FPGA working like this is to reprogram the flash memory on the board, and power cycle the whole system. That way the FPGA loads from on-board Flash, though note that this _must_ happen very quickly within the recommended PCIe power up time, so that the motherboard can detect the new device.

Obviously, it would be very useful if we could force the motherboard to do a PCIe rescan to detect a new configuration after a reprogram. There is a stack overflow thread about this here. But note that none of the methods there seem to work in all circumstances, but you might be in luck. The method suggested in the previous answer seems a bit chancy to me ..

A really useful technique would be to use partial reconfiguration. That is, that the PCIe part of your design is left intact, and just reconfigure the customised part of the design. That way, the PCIe link would not be dropped, and development would be a lot easier.

In fact, one could go further, and connect a port from the PCIe part to the internal reconfiguration interface, so that the partial reconfiguration can be performed over the PCIe bus itself.

.. and guess what, this is exactly what the Alveo acceleration cards do. Now you would think that such an IP block would be made freely available in the IP catalogue, but no such luck I'm afraid.

 

 

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Visitor
Visitor
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Registered: ‎03-31-2019

Yes this rescan method actually worked for me and has been consistently. Yes you are right, the more proper solution is to utilize the ultrascale's "tandem configuration" feature. It will load a "slimmed down" version of the pcie instance in a short time to establish connection while configuring the rest of the fpga, which they claim will take less than 120ms, which is within the required time for the pcie endpoint to reconnect.

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