01-29-2020 04:58 PM
I'm trying to use the XDMA in stream mode. If i want to use the Axis switch with h2c in the slave and multiple masters how would I implement something like that? Would I be able to select the master I want to route the slave to? Any examples would be appreciated.
02-03-2020 08:24 AM
With AXI4-Stream interconnect, you can use “Control register routing” for your use case. I highlighted it in the snapshot below. This option enables a S_AXI_LITE interface on the interconnect IP.
To control the routing from S_AXI to one of the M_AXI ports on the AXI4-stream interconnect, you will need to write to the register space of AXI4 stream interconnect IP. Please check “Register Space” section in page 26 of PG085 at the link below.
02-03-2020 09:55 AM
@venkata So I connected the M_AXI_LITE from XDMA to S_AXI_LITE of interconnect. Using the Xilinx provided drivers, I'm doing the below but not getting the expected results
TEST 1: route S00_AXIS to M00_AXIS, expect data from XDMA_H2C to route to M00_AXIS output
#setup switch to route S00 to M00
reg_rw /dev/xdma0_user 0x40 w 0x0
# Commit registers, Write address offset 0x0, data 0x2
reg_rw /dev/xdma0_user 0x00 w 0x2
/dma_to_device -d /dev/xdma0_h2c0/ -f datafile.bin -s 1024 -c 1
I have ILAs set on S_AXI_LITE, S00_AXIS, M00_AXIS, and M01_AXIS; when I setup the switch, i see data on the S_AXI_LITE, but then when i do the dma_to_device nothing on M00_AXIS.
02-05-2020 08:28 AM
Have you checked that DMA transfer is successful to XDMA IP output - m_axis_h2c_* interface (or) S00_AXIS of the AXI-Stream interconnect?