cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
darin_i
Participant
Participant
600 Views
Registered: ‎02-15-2018

XDMA v4.1 bypass generates write cycles, but not reads

Hi,

 

I'm having a strange problem with the xdma v4.1 IP on a Kintex-7 part (on a PCIe card with integrated PCIe Gen 2 I/F) and a memory-mapped design.

 

I'm trying to build a radar data simulator, the basic idea behind which is that the user can load simulated ADC data of their choice into DDR3 memory (on the card) via the BAR bypass interface and then stream it out at a certain rate to test processing algorithms. I plan to use the AXI Datamover to simulate incoming ADC data from the (not-yet-built) radar unit.

 

I decided to start 'easy' and set up the xdma IP in memory-mapped mode, and got the thing working with a bram-based design. I can store data into the bram and DMA it out quite happily.

 

When I removed the bram and threw a MIG block in to control the DDR3, I can no longer generate READ activity on the bypass bus (as observed with a system_ila block) but I can still generate WRITE traffic.

Any thoughts?
 
Thanks
 
  -darin
1 Reply
venkata
Moderator
Moderator
538 Views
Registered: ‎02-16-2010

Can you share the system_ila capture when you initiate read activity?
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Reply