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dpeti
Visitor
Visitor
4,111 Views
Registered: ‎10-05-2007

Xapp859 fifo interface

Hello,

 

I would like to ask some help regarding this PCI Express DMA controller.

I'd like to replace the DDR2 MPMC interface with NPI interface, but I stucked a little bit:

 

As a first step I wanted to fool the DMA controller with constant "FIFO" data, as automatically ACKing read and write requests, and signaling NotEmpty Read and NotFull and AlmostFull Write FIFO-s.

 

I've put KEEP property to all signals to debug it with chipscope.

 

 

reg iack;
reg eack;
reg [2:0] dmastate;
reg [127:0] idata;
reg [127:0] edata;

assign pause_read_requests			= 0;

assign ingress_data_ack = iack;
assign egress_data_ack = eack;

assign egress_data = 128'hABCD0123ABCD0123ABCD0123ABCD0123;

assign ingress_fifo_status = 0;
assign egress_fifo_status = 3'b100;


localparam IDLE  = 3'b000;
localparam LOADE = 3'b001;
localparam LOADI = 3'b010;
localparam DONE  = 3'b011;

always @(posedge trn_clk)
	begin
	idata <= ingress_data;
	edata <= egress_data;
	end

always @(posedge trn_clk)
begin
	if (trn_reset)
		begin
			dmastate <= IDLE;
			iack <= 0;
			eack <= 0;
		end
	else
		begin
			case (dmastate)
			IDLE:		begin
							iack <= 0;
							eack <= 0;
							if (ingress_data_req)
								begin
									dmastate <= LOADI;
									iack <= 1;
								end
							else if (egress_data_req)
								begin
									dmastate <= LOADE;
									eack <= 1;
								end
							else
								begin
									dmastate <= IDLE;
								end
						end
						
			LOADE:	begin
							dmastate <= DONE;
							eack <= 0;
						end
						
			LOADI:	begin
							dmastate <= DONE;
							iack <= 0;
						end
						
			DONE:		begin
							dmastate <= DONE;
							eack <= 0;	
							iack <= 0;							
						end	
						
			default:	begin
							dmastate <= DONE;
							eack <= 0;	
							iack <= 0;							
						end
			endcase
		end
end	

The PC recognises the HW and successfully installs the driver, but when I start the program (wd910_csharp_capp859.exe) first it does nothing (so I kill it with task manager) and then it says that read start bit set, so I cannot run read DMA.

 

During chipscope debugging I've found that during the first program start, somehow it starts a Read DMA request, but it doesn't complete (addresses is not increasing, first address just loaded, and then it does nothing).

 

You can find a chipscope debug window attached.

 

 

2.jpg
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2 Replies
dpeti
Visitor
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4,055 Views
Registered: ‎10-05-2007

The code above is a little bit buggy, but I debugged it, and the problem probably will be in the read request module.

 

After starting the program, it sends a read dma signal to the core, and the core generates the following read requests (and it doesn't get any completion packet for it):

 

0000 2020 0000 00FF        0850 D000 0000 0000 - read request (trn_td)

0 00 00000 0 000 0000    R,MemoryReadRequest(Fmt00,Type00000),R,TC(BestEffort000),R
0 0 10 00  0000100000    TD(NoDigest0),EP(NotPoisoned0),Attr(RelaxedOrdering1,HwEnforcedCahceCoherencyExpected0),At(UntranslatedAddr00),Length(0x20)
0000000000000000    Requester ID
00000000 1111 1111    Tag, LastDW BE, 1stDW BE


0000100001010000    Address
1101000000000000    Address
0000000000000000    Address
0000000000000000    Address

 

 

Is it correct that the Requester ID is zero?!

I think it should be come from the cfg_{bus,device,function}_number...

Someone confirm it, please!

Thank you!

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dpeti
Visitor
Visitor
4,014 Views
Registered: ‎10-05-2007

Ok, it was user error (as usual)

I havent noticed the pcie_id inputs :)

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