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Visitor
Visitor
2,458 Views
Registered: ‎02-13-2018

Xilinx_Answer_65444 performance test failed

Hi Tech Support:

 

I have vcu118 board. According to 

https://www.xilinx.com/support/answers/65444.html

 

run_test.sh is Ok after address offset for dma is added.

 

but run  perform_hwcount.sh, it will give data transfered == 0 as below:

 

Saw video from 

https://www.xilinx.com/video/technology/getting-the-best-performance-with-dma-for-pci-express.html

 

The demo in the time of 5:29 of 13:05. told that perform_hwcount.sh runs good after perform_hwcount.sh is changed but demo don't tell us how to change.

 

Can the support give us upon how to change perform_hwcount.sh to make test work.

 

Thanks 

Frank

 

The output info as below:

 

device = /dev/xdma0_c2h_0, size = 0x00400000, count = 1
IOCTL_XDMA_ADDRMODE_SET failed.
IOCTL_XDMA_PERF_START succesful.
IOCTL_XDMA_PERF_GET succesful.
perf.transfer_size = 4194304
perf.iterations = 0
(data transferred = 0 bytes)
perf.clock_cycle_count = 165
perf.data_cycle_count = 4
(data duty cycle = 2%)
IOCTL_XDMA_PERF_STOP succesful.
perf.transfer_size = 4194304 bytes
perf.iterations = 0
(data transferred = 0 bytes)
perf.clock_cycle_count = 165
perf.data_cycle_count = 4
(data duty cycle = 2%)
data rate ***** bytes length = 4194304, rate = 0.024242
perf.pending_count = 0

 

 

 

 

 

 

 

 

 

 

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9 Replies
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Moderator
Moderator
2,394 Views
Registered: ‎02-16-2010

Re: Xilinx_Answer_65444 performance test failed

Are you using XDMA IP example for this test? Can you share the .xci file of the IP?
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Moderator
Moderator
2,370 Views
Registered: ‎02-16-2010

Re: Xilinx_Answer_65444 performance test failed

Can you enable the debug logging with the driver? Share the log generated with it.

I have captured the guidance to do this from AR#65444 document.

Enabling Debug Messaging in the Driver
To aid development and debug of the PCIe DMA driver, you can enable debug messaging by setting the XDMA_DEBUG define to 1. To make this modification, open the include/xdma-core.h file and search for the #define that sets the XDMA_DEBUG variable to 0. Change the ‘0’ to a ‘1’ as shown below.
#define XDMA_DEBUG 1
Once modified, the driver must be uninstalled, recompiled, and reinstalled by following the directions in the Loading the Driver section. You can view the messages from the kernel driver by using the Linux dmesg command.
$Linux> dmesg
This can be used to debug failures or to view the DMA operational messages.
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Visitor
Visitor
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Registered: ‎02-13-2018

Re: Xilinx_Answer_65444 performance test failed

Hi Venkata:

 

xdma is used and enable XDMA_DEBUG 1

 

The .xci and dmesg log is attached.

 

Could you please check why "data transferred = 0 bytes"?

 

how do I know axi lite bus address? 

 

I use 7z to zip the file because it is too big.

 

Thanks and best regards

Frank

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Visitor
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2,339 Views
Registered: ‎02-13-2018

Re: Xilinx_Answer_65444 performance test failed

 
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Visitor
Visitor
2,328 Views
Registered: ‎02-13-2018

Re: Xilinx_Answer_65444 performance test failed

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Visitor
Visitor
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Registered: ‎02-13-2018

Re: Xilinx_Answer_65444 performance test failed

Hi Venkata:

 

I have attached the log already. 

 

Do you need anything more from my side.

 

Thanks

Frank

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Xilinx Employee
Xilinx Employee
2,142 Views
Registered: ‎12-10-2013

Re: Xilinx_Answer_65444 performance test failed

Hi Frank,

 

I wanted to let you know we have created SR 10429894 and assigned it to an engineer.  He will be running the same tests on VCU118 with your configuration, and we are currently reviewing the logs as well.   We will be in touch via the SR shortly.

 

Sincerely,

Beth

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Xilinx Employee
Xilinx Employee
1,998 Views
Registered: ‎12-10-2013

Re: Xilinx_Answer_65444 performance test failed

Solution / Update on topic:

 

We have found two issues in the setup.

 

1) A SmartConnect was being used between the DMA/Bridge Subsystem and the DDR.  We have found that these two IP are not compatible due to design decisions in the SmartConnect, and we do not recommend using any PCIe IPs with SmartConnect at this time.   This may change in the future, however today we would only recommend using an Interconnect IP to connect in the IPI infrastructure to PCIe IPs (all) for the full AXI data path. 

 

2) While the IO tests provided with AR65444 allow the user to set an AXI address offset for the targeted memory interface location (like offset 0x8000_0000 shown in the video), the Performance test does not have this switch available.  A CR has been filed to resolve this issue in a future release. 

 

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Xilinx Employee
Xilinx Employee
1,880 Views
Registered: ‎05-06-2008

Re: Xilinx_Answer_65444 performance test failed

Hello Fzhu129,

Did this issue get resolved?

If so, can you mark the correct response as an accepted solution?

If you have more questions, please let me know.

Thank you,
Chris

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