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rkvr
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Adventurer
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Registered: ‎07-23-2019

Xilinx Root port Lane swapping support

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Hello,

I am trying to do lane swapping for xilinx root port due in hardware lane are swapped between FPGA GTH pin and connector.

But constraint specified in xdc file are not changing pin location/swaping lane. I am getting warning during implementation, user specified constraint overwritten by ip constraint.

Thanks,

 

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garethc
Moderator
Moderator
472 Views
Registered: ‎06-29-2011

Hi @rkvr 

When creating a post can you please provide more details as the answer could be different depending on the device you are using 7-Series, US/US+ etc.

e.g. Note: When initiating a forum post, please don’t forget to mention the following details at the start: 

  • Vivado Version (e.g. 2018.2, 2019.2 etc.)
  • Name of the IP (e.g. UltraScale+ Devices Integrated Block for PCI Express, DMA/Bridge Subsystem for PCI Express (Bridge Mode), DMA/Bridge Subsystem for PCI Express (DMA mode) etc.)
  • Device Family (e.g. Virtex Ultrascale+, Kintex Ultrascale etc.)

This is detailed in the PCIe and CPM Board - Useful Resources sticky post that is seen at the top of the board when you are on it. You should always review this before posting and below is a link to it.
https://forums.xilinx.com/t5/PCIe-and-CPM/PCIE-and-CPM-Useful-Resources/m-p/1079558/highlight/true#M15894

The following is some details that I have for 7-series that might help you.
****************************************************************************************************************************************
(Example solution from xc7vx690tffg1761-2, but applies to all 7-Series in Vivado)

**** THIS IS FOR x4 LINK ****
--------------------------------------------------------
Solution 1 - Forcing change at top XDC
-------------------------------------------------------
Description - To override the located and managed feature of the PCIe core created XDC, with recommended Pin locations as described in the IP Core Product Guides, you must first un-LOC the channels, then move the channels to a different quad (GT), then move them back.  Sequentially.   Drawback:  If you need to use all the other possible GTs, then this methodology will not work.

Example addition to top level XDC, for swapping a x4 PCIe bus.   (Originally X1Y11 = Lane[0], and so on)

#########################################################################################################################
# PCIE Core Constraints
#########################################################################################################################
set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

# PCIe Lane 0
set_property LOC GTHE2_CHANNEL_X1Y7 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 1
set_property LOC GTHE2_CHANNEL_X1Y6 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 2
set_property LOC GTHE2_CHANNEL_X1Y5 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 3
set_property LOC GTHE2_CHANNEL_X1Y4 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]

# PCIe Lane 3
set_property LOC GTHE2_CHANNEL_X1Y11 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 2
set_property LOC GTHE2_CHANNEL_X1Y10 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 1
set_property LOC GTHE2_CHANNEL_X1Y9 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 0
set_property LOC GTHE2_CHANNEL_X1Y8 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]

###############################################################################

-----------------------------------
Solution #2 - Edit core XDC file outside of the Vivado environment  (while maintaining a DCP flow
----------------------------------
Drawback - Any time you regenerate the core, regenerate output products, or **UPGRADE** the core, this edit will need to be repeated

a)    Generate the core, generate output products (DCP is fine)
b)    Navigate to <project>/<project>.srcs/sources_1/ip/pcie3_7x_0/sources/  outside of the Vivado enviroment
c)    Outside of the Vivado environment, edit the pcie3_7x_0-PCIE_X0Y0.xdc, just changing the 0, 1, 2, 3 to 3, 2, 1, 0 in lines 75 - 81 (odd)
c)    Save
d)    Back in Vivado, In your design runs window (bottom of tool screen), go to the "Out-of-Context Module Runs" list, right click on the synth_1 for the core, and select "Reset Runs"
e)    Right click on the same line and select "Launch Runs"

Once this is completed, you know have a DCP core with those constraints.

Warnings: This may result in timing issues, or unstable link if the link partner does not support lane reversal. 
****************************************************************************************************************************************

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

2 Replies
garethc
Moderator
Moderator
473 Views
Registered: ‎06-29-2011

Hi @rkvr 

When creating a post can you please provide more details as the answer could be different depending on the device you are using 7-Series, US/US+ etc.

e.g. Note: When initiating a forum post, please don’t forget to mention the following details at the start: 

  • Vivado Version (e.g. 2018.2, 2019.2 etc.)
  • Name of the IP (e.g. UltraScale+ Devices Integrated Block for PCI Express, DMA/Bridge Subsystem for PCI Express (Bridge Mode), DMA/Bridge Subsystem for PCI Express (DMA mode) etc.)
  • Device Family (e.g. Virtex Ultrascale+, Kintex Ultrascale etc.)

This is detailed in the PCIe and CPM Board - Useful Resources sticky post that is seen at the top of the board when you are on it. You should always review this before posting and below is a link to it.
https://forums.xilinx.com/t5/PCIe-and-CPM/PCIE-and-CPM-Useful-Resources/m-p/1079558/highlight/true#M15894

The following is some details that I have for 7-series that might help you.
****************************************************************************************************************************************
(Example solution from xc7vx690tffg1761-2, but applies to all 7-Series in Vivado)

**** THIS IS FOR x4 LINK ****
--------------------------------------------------------
Solution 1 - Forcing change at top XDC
-------------------------------------------------------
Description - To override the located and managed feature of the PCIe core created XDC, with recommended Pin locations as described in the IP Core Product Guides, you must first un-LOC the channels, then move the channels to a different quad (GT), then move them back.  Sequentially.   Drawback:  If you need to use all the other possible GTs, then this methodology will not work.

Example addition to top level XDC, for swapping a x4 PCIe bus.   (Originally X1Y11 = Lane[0], and so on)

#########################################################################################################################
# PCIE Core Constraints
#########################################################################################################################
set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

set_property is_bel_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]]
set_property is_loc_fixed false [get_cells [list {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]]

# PCIe Lane 0
set_property LOC GTHE2_CHANNEL_X1Y7 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 1
set_property LOC GTHE2_CHANNEL_X1Y6 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 2
set_property LOC GTHE2_CHANNEL_X1Y5 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 3
set_property LOC GTHE2_CHANNEL_X1Y4 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]

# PCIe Lane 3
set_property LOC GTHE2_CHANNEL_X1Y11 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 2
set_property LOC GTHE2_CHANNEL_X1Y10 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 1
set_property LOC GTHE2_CHANNEL_X1Y9 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]
# PCIe Lane 0
set_property LOC GTHE2_CHANNEL_X1Y8 [get_cells {pcie3_7x_0_support_i/pcie3_7x_0_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]

###############################################################################

-----------------------------------
Solution #2 - Edit core XDC file outside of the Vivado environment  (while maintaining a DCP flow
----------------------------------
Drawback - Any time you regenerate the core, regenerate output products, or **UPGRADE** the core, this edit will need to be repeated

a)    Generate the core, generate output products (DCP is fine)
b)    Navigate to <project>/<project>.srcs/sources_1/ip/pcie3_7x_0/sources/  outside of the Vivado enviroment
c)    Outside of the Vivado environment, edit the pcie3_7x_0-PCIE_X0Y0.xdc, just changing the 0, 1, 2, 3 to 3, 2, 1, 0 in lines 75 - 81 (odd)
c)    Save
d)    Back in Vivado, In your design runs window (bottom of tool screen), go to the "Out-of-Context Module Runs" list, right click on the synth_1 for the core, and select "Reset Runs"
e)    Right click on the same line and select "Launch Runs"

Once this is completed, you know have a DCP core with those constraints.

Warnings: This may result in timing issues, or unstable link if the link partner does not support lane reversal. 
****************************************************************************************************************************************

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

rkvr
Adventurer
Adventurer
417 Views
Registered: ‎07-23-2019
Hi Gareth,

Solution 1 works for me.

The drawback you mention is having workaround and that is also worked for me. following is example constraint
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]

set_property LOC GTHE4_CHANNEL_X0Y20 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X0Y21 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X0Y22 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X0Y23 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[5].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]


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