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Xilinx® Training on PCIe Design

How to Design a Xilinx Connectivity System in 1 Day - Updated December 2013

This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of serial transceivers, PCIe® technology, memory interfaces, and Ethernet MACs. Design examples and labs show components from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights usage of the serial transceivers. - Read More

PCIe Protocol Overview - Released March 2011

This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe® architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed. Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course. - Test Your Knowledge

Designing a LogiCORE PCI Express System - Updated October 2012

Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect. - Test Your Knowledge

Play Video 7-Series Dedicated Hardware
This video introduces the dedicated hardware resources available in the 7-Series FPGAs. The features described include the dedicated Serial Gigabit Transceivers, PCI Express core, and XADC resources.

Updated: Sept 2012
Play Video Reducing System Power & Cost with Artix-7 FPGAs
In this video you will learn about overall system power and cost with Artix-7 FPGAs. We’ll quickly review the Artix-7 FPGA architecture, logic fabric, 4th gen DSP48E1 slice, 6.6 Gbps GTP transceivers, PCIe Gen2 hard block, memory interface, analog interface, applications overview, and where you can learn more.

Released: Feb 2013
1 Reply
Registered: ‎06-29-2011

Good PCIe content.




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