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zainnvbi
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Registered: ‎10-04-2018

ZC706 and ZCU102 communication via PCI express

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Hi everybody,

I configured the PS on ZCU102 as the PCIe root complex with 4 lane and load petalinux 2018.2 on the ZynqMP processor (exactly as presented here). Additionally, a ZC706 board is configured as a simple communication controller endpoint (the example design presented here). 

Now am going to connect ZC706 and ZCU102 via PCIe slot. After the petalinux is booted successfully, it seems the OS does not recognized the device (ZC706). I check this by this command

 

root@farzian:~# echo 1 > /sys/bus/pci/rescan
[ 48.979275] pci 0000:00:00.0: PCI bridge to [bus 01-0c]

Note that when I plug the programmed zc706 to my pc motherboard, Windows7 recognizes it and I can explore the configuration address space of the device. But in petalinux, I can't see the device.

Can anybody help me?

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zainnvbi
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Registered: ‎10-04-2018

Hi @bethe,

The problem was solved. That was my mistake making gt_refclk  connection between PCIe finger and proper FPGA pins. 

 

Thank you so much.

View solution in original post

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @zainnvbi,

 

Is your ZC706 FPGA programmed (DONE bit high) prior to your ZCU102 powering on?   This could be a load time issue.   If that isn't the case, could you check the LTSSM state on the ZC706 to see where training got to?   You could do this via JTAG debugger added to the core, or ILA. 

 

What is lspci -vvv showing?

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zainnvbi
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Registered: ‎10-04-2018

Hi @bethe, Thank you for the reply.

The power of ZC706 is provided via PCIe finger connected to zcu102 and the power input of zc706 is connected to ATX power of zcu102. When I power on zcu102, both boards are programmed from sd card (zcu102 ) and flash (zc706). I then press "prog" push button on zcu102 to make sure the zc706 is programmed before the zcu102 boots from it's sd card.

 

Here is the lspci -vvv command's output:

 

root@zcu_pci_enabled:/sys/bus/pci# lspci -vvv
00:00.0 PCI bridge: Xilinx Corporation Device d021 (prog-if 00 [Normal decode])
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 255
Region 0: Memory at e0000000 (64-bit, non-prefetchable) [disabled] [size=256M]
Bus: primary=00, secondary=01, subordinate=0c, sec-latency=0
I/O behind bridge: 00000000-00000fff [size=4K]
Memory behind bridge: fff00000-000fffff [empty]
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [empty]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [60] Express (v2) Root Port (Slot-), MSI 00
DevCap:MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl:Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta:CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend+
LnkCap:Port #0, Speed 5GT/s, Width x4, ASPM not supported
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl:ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta:Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible+
RootCap: CRSVisible+
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [10c v1] Virtual Channel
Caps:LPEVC=0 RefClk=100ns PATEntryBits=1
Arb:Fixed- WRR32- WRR64- WRR128-
Ctrl:ArbSelect=Fixed
Status:InProgress-
VC0:Caps:PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb:Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl:Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status:NegoPending- InProgress-
Capabilities: [128 v1] Vendor Specific Information: ID=1234 Rev=1 Len=018 <?>

  

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bethe
Xilinx Employee
Xilinx Employee
1,212 Views
Registered: ‎12-10-2013

Hi @zainnvbi,

 

Since the EP is being powered first, and not enumerating, could you please provide the JTAG debugger output I mentioned earlier?  This will allow us to see where it go to in training.

 

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zainnvbi
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Registered: ‎10-04-2018

Hi @bethe,

The problem was solved. That was my mistake making gt_refclk  connection between PCIe finger and proper FPGA pins. 

 

Thank you so much.

View solution in original post

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