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Visitor bralex
Visitor
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Registered: ‎02-26-2018

ZCU102: Access the same DDR region from PCIe and PS APU A53 failed

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Hello.

I am trying to access the DDR memory on ZCU102 from PCIe through ingress translation. Values received through PCIe and A53 are different.

1. ML605, connected to ZCU102, writes some value to BAR1 (32-bit, non-prefetchable memory, 64 KB).

2. C-application running on A53  (ZCU102) allocates ARRAY of chars, reads BAR1 value and configures ingress translation as follows:

    - src=BAR1 value;

    - DST = ARRAY address;

    - ARCACHE = 0;

    - AWCACHE = 0;

3. C-application running on A53  (ZCU102) writes 5 to 0-th element of ARRAY, and read it. Written value is 5.

4. C-application running on Microblaze (ML605) reads BAR1 by offset = 0 (it should be 0-th element of ARRAY on ZCU102 after translation). Value is 0. C-app on Microblaze writes value 6 and reads it back. Written value is 6. But in the same time A53 on ZCU102 reads value of 0-th element of ARRAY and the value is always 5.

 

So it looks like A53 (through AXI) and Microblaze (through PCIe) read and write to different memory regions.

If I do the same thing with GPU registers, it works. 

 

Does anybody know the reason for such behavior?

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Visitor bralex
Visitor
576 Views
Registered: ‎02-26-2018

Re: ZCU102: Access the same DDR region from PCIe and PS APU A53 failed

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It seems that there was a problem with memory allocation in linux at zcu102. The problem was solved by using udmabuf driver from user space application.

View solution in original post

3 Replies
Moderator
Moderator
841 Views
Registered: ‎02-16-2010

Re: ZCU102: Access the same DDR region from PCIe and PS APU A53 failed

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1. Whether ZCU102 is configured as Root Port?
2. Are you using PS-PCIe (or) PL-PCIe on ZCU102?
3. If ZCU102 is the RP, whether ML605 is detected by RP?
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Visitor bralex
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Registered: ‎02-26-2018

Re: ZCU102: Access the same DDR region from PCIe and PS APU A53 failed

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Thank you for reply.

1. ZCU102 is configured as EndPoint

2. I am using PS-PCIe on ZCU102

 

ZCU102 is detected by ML605 successfully. I can perform enumeration, read DMA registers or GPU registers (through ingress translation), but not DDR.

 

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Visitor bralex
Visitor
577 Views
Registered: ‎02-26-2018

Re: ZCU102: Access the same DDR region from PCIe and PS APU A53 failed

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It seems that there was a problem with memory allocation in linux at zcu102. The problem was solved by using udmabuf driver from user space application.

View solution in original post