08-20-2018 07:56 AM
I am developing video frame buffering on Ubunut host Via PCIe from Xilinx board (Test pattern generated). The IP used in this case is XDMA.
I tried to use the concept of dynamic linking. the FPGA is sending tlast correctly but
1. For buffer defined the end of packet is set
2. when there is loop back to first buffer from last (i.e. descriptor link to the first descriptor) then the end of packet is not available, even though the FPGA is sending tlast signal.
Can someone please guide me to the solution or implementation for video frame buffering for XDMA.
thank you in advance
08-21-2018 06:16 PM
08-28-2018 12:28 AM
Here is the block diagram
See ttachment for setting of DMA.
I can see Tlast signal send from sampleGenerater block at the last packate of 256bit (tvalid ='1' and tready='1'), but this is not recognized as EOP by DMA or driver in PC.
08-28-2018 12:07 PM