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Voyager
Voyager
649 Views
Registered: ‎10-31-2016

ZCU106: XDMA PCIe end of packet

Hello, 

 

I am developing video frame buffering on Ubunut host Via PCIe from Xilinx board (Test pattern generated). The IP used in this case is XDMA. 

 

I tried to use the concept of dynamic linking. the FPGA is sending tlast correctly but 

 

1. For buffer defined the end of packet is set 

2. when there is loop back to first buffer from last (i.e. descriptor link to the first descriptor) then the end of packet is not available, even though the FPGA is sending tlast signal.

 

Can someone please guide me to the solution or implementation for video frame buffering for  XDMA.

 

thank you in advance 

Best regards 

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3 Replies
Moderator
Moderator
616 Views
Registered: ‎02-16-2010

Re: ZCU106: XDMA PCIe end of packet

Can you please provide a block diagram of your design? It can help to understand the issue better.
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Voyager
Voyager
581 Views
Registered: ‎10-31-2016

Re: ZCU106: XDMA PCIe end of packet

Hi, 

 

Here is the block diagram 

Capture.PNG

See ttachment for setting of DMA.

 

I can see Tlast signal send from sampleGenerater block at the last packate of 256bit (tvalid ='1' and tready='1'), but this is not recognized as EOP by DMA or driver in PC.

 

Best regards 

Capture1.PNG
Capture2.PNG
Capture3.PNG
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Moderator
Moderator
568 Views
Registered: ‎02-16-2010

Re: ZCU106: XDMA PCIe end of packet

Are you setting EOP bit in the last descriptor in which end of the packet needs to be specified? Please check Table 2-5 of PG195.
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