I have 2 Zynq systems running Linux connected via a AXI Memory Mapped to PCI Express IP to a USB Host Controller. The AXI Memory Mapped to PCI Express IP is configured as a Root Port. I have 3 cases:
The AXI-PCIe BAR Translation is always 0x00000000. Everything else except the BAR0 size configuration stays the same.
Can somebody explain to my how the BAR0 size configuration and the Zynq RAM size are connected?How should PCIE:BARs BAR0 actually be configured?
Thank you very much in advance!
Could you review this AR:https://www.xilinx.com/support/answers/70702.html ?
Not sure if it would help; please make sure issues discussed, if any relevant, are addressed.