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Observer
Observer
258 Views
Registered: ‎06-13-2019

Zynq AXI PCI Express, BAR0 size and RAM size connection

Hello!

I have 2 Zynq systems running Linux connected via a AXI Memory Mapped to PCI Express IP to a USB Host Controller. The AXI Memory Mapped to PCI Express IP is configured as a Root Port. I have 3 cases:

  1. Zynq with 512MB RAM and PCIE:BARS BAR0 size configured for 512MB --> PCIe communication with USB Host Controller is working
  2. Zynq with 1024MB RAM and PCIE:BARS BAR0 size configured for 512MB --> PCIe communication with USB Host Controller is not working
  3. Zynq with 1024MB RAM and PCIE:BARS BAR0 size configured for 1024MB --> PCIe communication with USB Host Controller is working

The AXI-PCIe BAR Translation is always 0x00000000. Everything else except the BAR0 size configuration stays the same.

Can somebody explain to my how the BAR0 size configuration and the Zynq RAM size are connected?
How should PCIE:BARs BAR0 actually be configured?

Thank you very much in advance!

Kind regards
Stefan

 

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Xilinx Employee
Xilinx Employee
181 Views
Registered: ‎08-06-2008

Could you review this AR:https://www.xilinx.com/support/answers/70702.html ?

Not sure if it would help; please make sure issues discussed, if any relevant, are addressed.

Thanks.

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