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Raoul
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Registered: ‎03-17-2021

Zynq MPSOC Cant get PS-PCIe to link up

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Hello, I am trying to use the PS-PCIe block on a Zynq ultrascale+. I am using Vivado and Vitis version 2020.1.

Unfortunetly, I can't get the PCIe port to link-up, I tested the hardware using another FPGA module and then linking-up does work. The only major functional difference between the two is that the Zynq uses a reset that is sourced from the PCIe port, while the other fpga uses an internally created soft-reset.

In the PCIe status register I can see that phy_rdy does become one but pcie_link_up does not. I believe that this tells me that I at least get a ref-clock. I tried this while the reset was disconnected and I get the same result. Is there anyway in which I can see if the PS-PCIe port actually resets?

I tried debugging using IBERT GTR but it doesn't really give my any new insights. As far as I understand it just tells me that I have a refclock coming in.

Raoul_0-1616506774650.png
Are there any other debug tools that I can use for debugging the PS-PCIe?

Thanks in advance for your help.

 

On a side note: I do get a serial message back when booting up that says: "PMU-FW is not running, certain applications may not be supported.". This isn't a problem when just using PCIe, right?

 

 

 

 

 

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pvenugo
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Moderator
432 Views
Registered: ‎07-31-2012

@Raoul ,

For PS PCIe are you using MIO reset provided by default or is it EMIO reset?

Refer to PS_PL_PCIe_Drivers_Debug_Guide.pdf   and check if hardware settings are done as per doc and review the software registers.


Regards

Praveen

 


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1 Reply
pvenugo
Moderator
Moderator
433 Views
Registered: ‎07-31-2012

@Raoul ,

For PS PCIe are you using MIO reset provided by default or is it EMIO reset?

Refer to PS_PL_PCIe_Drivers_Debug_Guide.pdf   and check if hardware settings are done as per doc and review the software registers.


Regards

Praveen

 


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Don’t forget to reply, kudo, and accept as solution.
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