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Contributor
Contributor
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Registered: ‎05-07-2017

Zynq MPSoC PS PCIe refclk config in FSBL.

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We have a custom board using zynq MPSoC PS side PCIe. The PCIe works as an RC. The reference clock for GTR lanes comes from a configurable clock generator. When we config clock using I2C in fsbl, the PCIe doesn't work properly (sometimes it works, sometimes, it doesn't).  When we use external clock (clock ready before we power on ZYNQ board, the PCIe works well.

Is it necessary for the clock ready before power on Zynq/PCIe module? 

 

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Moderator
Moderator
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Registered: ‎01-15-2008

pcie card to be detected in system during boot up is ~ 100ms, so if the GTR ref clock is not available during this time then you might see failures 

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Moderator
Moderator
348 Views
Registered: ‎01-15-2008

pcie card to be detected in system during boot up is ~ 100ms, so if the GTR ref clock is not available during this time then you might see failures 

View solution in original post

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Contributor
Contributor
339 Views
Registered: ‎05-07-2017

Thank you. we solved the problem by OTP the clock.

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