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Visitor
Visitor
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Registered: ‎07-18-2016

Zynq PCIe reference clock specification

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Hi,

 

   what is the min/max differential voltage specification for the PCIe reference clock input to a Zynq based PCIe Endpoint.?

 

Regards,

 

    Elwyn

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @hughese

 

you are welcome.

if you are using 7015, then Table 86 in DS187 applies.

 

Thanks,

Boris

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @hughese

 

if you are using Zynq Ultrascale+, you can refer to ds925 Table 97 for valid voltage range of PCIe ref clock

http://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

 

if you are using Zynq-7000 devices, you can refer to Table 90 in ds191 (XC7Z030-XC7Z045) or Table 86 in ds187 (XC7Z010-XC7Z020)

http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf

http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

 

Thanks,

Boris

 

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Visitor
Visitor
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Registered: ‎07-18-2016

Hi,

 

  perfect - thanks!

 

  I had found a lot of generic values but just needed to confirm the 7015 specs.

 

Regards,

 

    Elwyn

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Xilinx Employee
Xilinx Employee
983 Views
Registered: ‎08-07-2007

hi @hughese

 

you are welcome.

if you are using 7015, then Table 86 in DS187 applies.

 

Thanks,

Boris

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