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Contributor
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Registered: ‎01-09-2017

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Advisor evgenis1
Advisor
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Registered: ‎12-03-2007

Re: about zynq pcie

Hi @kaesar , 

 

Your IBERT test only shows the state of the Rx link from PCIe device to FPGA. The state of Tx link from FPGA to the device is unknown, and might be causing the issue.

 

There is a signal called cfg_ltssm_state[5:0]. It's an output from PCIe core, and very useful for debugging various issues. If PCIe link is good, this signal should be in 'L0'. If there are signal integrity issues, the link would periodically go to 'Recovery' for a few microseconds, then back to 'L0'. It might be that in your case it never reaches 'L0'. So it's worth taking a look at cfg_ltssm_state[5:0].

 

Thanks,

Evgeni

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Contributor
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Registered: ‎01-09-2017

Re: about zynq pcie

 
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Advisor evgenis1
Advisor
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Registered: ‎12-03-2007

Re: about zynq pcie

Hi @kaesar,  

 

Another thing to check is PERST# coming into PCIe controller. Make sure it's not active.

 

Thanks,

Evgeni

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Contributor
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Registered: ‎01-09-2017

Re: about zynq pcie

 
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Xilinx Employee
Xilinx Employee
1,260 Views
Registered: ‎08-02-2007

Re: about zynq pcie

Have you checked the rxelecidle and txelecidle

txelecidle is always asserted it means it is not able to detect the host

it could be an issue with connecttion (tx/rx swithed for example)

or you can try to bypass the detection by modify the code in the pipe_wrapper file

 

for example

Add the following
    wire        [(PCIE_LANE*3)-1:0]        int_RxStatus;
    reg          [(PCIE_LANE*3)-1:0]       reg_RxStatus;
   
   always @*
   begin
   if (PIPE_TXDETECTRX)
     reg_RxStatus <= 24'b011011011011011011011011;
   else
     reg_RxStatus <= int_RxStatus;
   end

  assign gt_rxstatus = reg_RxStatus;
  
   // Change the following
  .GT_RXSTATUS                    (gt_rxstatus[(3*i)+2:(3*i)]),
   // to
  .GT_RXSTATUS                    (int_RxStatus[(3*i)+2:(3*i)]),

 

 

Or you need to follow AR56616

 

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Contributor
Contributor
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Registered: ‎01-09-2017

Re: about zynq pcie

 
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Contributor
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Registered: ‎01-09-2017

Re: about zynq pcie

 
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Xilinx Employee
Xilinx Employee
1,215 Views
Registered: ‎08-02-2007

Re: about zynq pcie

it means  the link patiner has detected first 2 lanes but the FPGA has not  detected the link patiner

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: about zynq pcie

Please run set_property  is_locked true [ get_files xxx.xci ]

if there is a subIP inside, you will run the same for the subIP

edit the files in other text editor, and reload them into vivado

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