05-10-2019 12:42 AM
I instance an AXI-bridge for PCIe IP in Vivado 2018.1. In the simulation, our design sends a memory read request to host through AXI slave port on the PCIe IP. We observe a PCIE_MRD TLP transmitted with attr=0 from card to the host, and the host sends back a completion TLP with attr=1. Then, the PCIe IP hangs with cfg_local_error_out = 5'b10010 (Unexpected Completion Received). From the PCIe spec. 4.0, it says the Function is permitted to set the ID-Based Ordering (IDO) bit (Attr) of Completions it returns. The simulation goes well after we force the host always sets Attr=0 for completion TLP. In Vivado 2017.3, this issue doesn't happen. Is that a bug in this version?
(The detail of register, IDO Completion Enable, is shown in the following)
"IDO Completion Enable – If this bit is Set, the Function is permitted to set the ID-Based Ordering (IDO) bit (Attr) of Completions it returns (see Section 220.127.116.11 and Section 2.4). Endpoints, including RC Integrated Endpoints, and Root Ports are permitted to implement this capability. A Function is permitted to hardwire this bit to 0b if it never sets the IDO attribute in Completions. Default value of this bit is 0b."
05-20-2019 02:59 AM
What device are you using and what IP? Is this 7 series with AXI PCIe Gen2 Bridge or US/US+ with XDMA in bridge mode or AXI PCIe Gen3 Bridge?
Also is this seen with the out of the box example design that is provided with the IP you are using?
Note that the 'cfg_local_error_out' signal is not reliable if the usr clk and the core clk are different. Is this the case in your design?
You can enable Advanced Error Reporting (AER) to decode the AER register to accurately detect errors in the PCIe block.
Can you check the Error Code Bits [12-15] of the Requester Completion? This will give us a better idea of what the error is.
10-15-2019 01:48 AM
Thanks for the reply.
We are using US+ (VCU1525) and AXI bridge mode is used.
The issue was happend in our enviroment instead of example disign.