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datangel
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Registered: ‎09-10-2010

axi_pcie_0 simulation error in modelsim with vivado 2013.3

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Hi, I am using modelsim to simulate axi_pcie_0 example design generated by vivado 2013.3. The device is virtex-7. It's Okay to start simulation in Vivado simulator. However, there are several errors in modelsim as below. I did the compile_simlib and simulation settings following the guide. It's successful when I simulate MIG example design. So I think it should not be a compile_simlib issue. # ** Error: e:/Xproject/TestSimple/Counter/axi_pcie_0_example/axi_pcie_0_example.srcs/sources_1/ip/axi_pcie_0/axi_pcie_v2_2/hdl/src/verilog/axi_pcie_v2_2_pcie_2_0_v6.v(1426): Module 'PCIE_2_0' is not defined. # ** Error: e:/Xproject/TestSimple/Counter/axi_pcie_0_example/axi_pcie_0_example.srcs/sources_1/ip/axi_pcie_0/axi_pcie_v2_2/hdl/src/verilog/axi_pcie_v2_2_s6_pcie_v2_2.v(1281): Module 'PCIE_A1' is not defined. My questions are: 1. I can only find PCIE_2_1_WRAP/PCIE_3_0_WRAP module in secureip library in modelsim. Why older PCIE ip is used in this example design? Is this a known issue for viado 2013.3? 2. How could I solve this problem? Thanks a lot! Best Wishes, Jonathan
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kotir
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Registered: ‎02-03-2010

Hi,

 

PCIE_A1 is Spartan-6 based premitive for PCIe hard core.

PCIE_2_0 is Virtex-6 based premitive for PCIe hard core.

PCIE_2_7 is 7-series based premitive for PCIe hard core.

 

The AXI pcie core is made as generic and based on the device choice parameters passed to the top levl of IP , corrusponding instantiations are compiled.

 

It could be something wrong in your environment, these device choice related parameters are not passed and simulator might be trying to compile for all ?

 

Can you check if this could be reason ?

 

Regards,

KR

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kotir
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Registered: ‎02-03-2010

Hi ,

 

 

This would happen if you do not have secureip library is not compiled into compiledlibs.

MIG does nto use any secureips so i thingk this might be reason for mig simulations passing.

 

Regards,

kR

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

HI,

 

Is this with example design and you did compiled teh libraries and mapped them correctly?

Are you using the compatible Questasim version for 2013.3 ?

You can find the version in Table 2-2: Compatible Third-Party Tools of below link

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_3/ug973-vivado-release-notes-install-license.pdf

 

Also please try with Vivado 2014.4 and if you see the same error please upload your .xci file for investigation.

 

 

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kotir
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Hi ,

 

In AXI PCIe core the all the hard block premitives instantiated in source files.

AXI PCIe has generics (`defines) to compile the PCIe premitive based on the device chosen for project.

 

I think in older tools , there was an issue with tool where it tried to look for secureip which is not used int he simulation but looks for it. It got resolved in latter tools.

 

I remember that when i tried to compile gt files which has GTP and GTX instances, even though the parameter are set such that GTX need to be compiled, the tool looks for GTP also.

 

You need to give compile_simlibs -family all -language all -library all

 

can you try it ?

 

 

Regards,

KR

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datangel
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Hi KR/vsrunga, Thanks for your quick reply. I have tried to re-compile the library using the command "compile_simlib -family all -language all -library all -simulator modelsim" and the errors keep unchanged. So could you let me know if PCIE_2_0 and PCIE_A1 are used in example design generated by later version vivado? Just want to make clear the reason before we spend much time to get the new version tool/license ready.
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datangel
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The simulator I am using now is modelsim SE 10.1c. ALthough not in the Table 2-2, I could see modelsim as a option in the "compile_simlib -help".
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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

The modules are required for example design as well, if compatible modelsim is not used there is high possibility to see such errors please use teh version specified in release notes and recheck.

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datangel
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Hi,
Sure, I will try with modelsim 10.2 later. But I have doubt that there will be these two IPs using new version modelsim. Now I have PCIE_2_1_WRAP and PCIE_3_0_WRAP in the secureip of modelsim. One experiment I have done before is that I changed the example design. PCIE_2_0 is modified to PCIE_2_1 and there will be only error left. Just FYI. Thanks a lot!
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kotir
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Registered: ‎02-03-2010

Hi,

 

PCIE_A1 is Spartan-6 based premitive for PCIe hard core.

PCIE_2_0 is Virtex-6 based premitive for PCIe hard core.

PCIE_2_7 is 7-series based premitive for PCIe hard core.

 

The AXI pcie core is made as generic and based on the device choice parameters passed to the top levl of IP , corrusponding instantiations are compiled.

 

It could be something wrong in your environment, these device choice related parameters are not passed and simulator might be trying to compile for all ?

 

Can you check if this could be reason ?

 

Regards,

KR

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datangel
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Hi KR,


I think you give the right reason! It seems that the source file include all these three cores in different generate blocks and 'C_FAMILY' parameter is used to select the right core during compiling. If I comment these two instantiations, it will pass the compile step and only X7 related modules will be there. It looks like modelsim need these modules even if they are in unused. Could you let me know if you know this is true?

So this problem should be a modelsim issue and I will go further into the simulation. BTW, I think you mean "PCIE_2_1 is 7-series based premitive for PCIe hard core", right?


Meanwhile, I have also tried to simulate with modelsim 10.2, it's the same result with 10.1.


Thanks very much!!
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