08-29-2019 04:08 AM
I am using ZCU106 , implemented Rootcomplex(xdma AXI Bridge) on PL, and attached PCIe EP device. It correctly enumerate wihtout any problem(I ink so) : Logs are here:
[ 4.274313] xilinx-pcie 400000000.axi-pcie: Using MSI FIFO mode
[ 4.279796] xilinx-pcie 400000000.axi-pcie: Base address 536870912
[ 4.285895] xilinx-pcie 400000000.axi-pcie: PCIe Link is UP
[ 4.291447] xilinx-pcie 400000000.axi-pcie: host bridge /amba_pl@0/axi-pcie@a0000000 ranges:
[ 4.299827] xilinx-pcie 400000000.axi-pcie: No bus range found for /amba_pl@0/axi-pcie@a0000000, using [bus 00-ff]
[ 4.310297] xilinx-pcie 400000000.axi-pcie: MEM 0xa0000000..0xafffffff -> 0x00000000
[ 4.318250] xilinx-pcie 400000000.axi-pcie: PCI host bridge to bus 0000:00
[ 4.324999] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 4.330449] pci_bus 0000:00: root bus resource [mem 0xa0000000-0xafffffff] (bus address [0x00000000-0x0fffffff])
[ 4.342773] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 4.350772] pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 4.359014] pci 0000:02:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 4.364452] pci 0000:02:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 4.376848] pci 0000:00:00.0: BAR 8: assigned [mem 0xa0000000-0xa00fffff]
[ 4.379156] pci 0000:01:00.0: BAR 8: assigned [mem 0xa0000000-0xa00fffff]
[ 4.385901] pci 0000:02:01.0: BAR 8: assigned [mem 0xa0000000-0xa00fffff]
[ 4.392650] pci 0000:03:00.0: BAR 0: assigned [mem 0xa0000000-0xa007ffff]
[ 4.399399] pci 0000:03:00.0: BAR 1: assigned [mem 0xa0080000-0xa0080fff]
[ 4.406146] pci 0000:03:00.0: BAR 2: assigned [mem 0xa0081000-0xa0081fff]
[ 4.412893] pci 0000:03:00.0: BAR 3: assigned [mem 0xa0082000-0xa0082fff]
[ 4.419641] pci 0000:03:00.0: BAR 4: assigned [mem 0xa0083000-0xa0083fff]
[ 4.426389] pci 0000:02:01.0: PCI bridge to [bus 03]
[ 4.431320] pci 0000:02:01.0: bridge window [mem 0xa0000000-0xa00fffff]
[ 4.438070] pci 0000:02:02.0: PCI bridge to [bus 04]
[ 4.443005] pci 0000:01:00.0: PCI bridge to [bus 02-04]
[ 4.448188] pci 0000:01:00.0: bridge window [mem 0xa0000000-0xa00fffff]
[ 4.454939] pci 0000:00:00.0: PCI bridge to [bus 01-04]
[ 4.460124] pci 0000:00:00.0: bridge window [mem 0xa0000000-0xa00fffff]
[ 4.466943] Error: Driver 'xilinx-pcie' is already registered, aborting...
[ 4.474754] ps_pcie_dma init()
I cant access any of BARs address which is 0xa0000000 from my driver so decided to use devmem for simple rd/wr,
devmem 0xA0000000 32
[ 3737.887887] xilinx-pcie 400000000.axi-pcie: Slave unsupported request
Note: (1) excluded "filter access to /dev/mem" in kernel configuration
(2) xdma ip configuration in PL, AXI to PCIe transalation: 0xa0000000 , I tried with 0x0 too, doesnt make any difference.
Let me know i fyou need any more information. I dont really understand why devmem cant access 0xA0000000. It does rd/wr on rootcomplex register which is on AXI_LITE bus.
08-29-2019 01:18 PM
Have you set "memory space enable" bit in the command register of the end point?
09-10-2019 08:59 AM - edited 09-10-2019 09:03 AM
@venkata sincere apologies for late reply as I was away from work for while.
Yes, This bit is set on EP and ep device works on windows and linux(0x86 PC). devmem works on ubuntu 0x86.
could you please explain AXI address translator little more. I am using xdma as a rootcomplex and I have set AXI to PCIe transalation: 0xa0000000, so if you use devmem 0xa0000000, how this translator react on this when i try to access BAR address? I guess something is wrong here.
09-11-2019 05:01 AM
10-24-2019 10:24 AM
Oscillator on board was generating too much jitter which was upsetting EP device but somehow PCIe device enumarete but doesnt allow to success any transaction. That was the reason. Now, I can access memory EP Bars.
11-28-2019 09:39 AM
I have the same issue: I cannot access EP BARs.
Would you please elaborate on how to reduce jitter for the oscillator? Thanks.
11-28-2019 09:54 AM
Are you using same zcu106 board with external xilinx FMC to pcie rootcomplex? If you using same board, read the board manual, you will see pushbutton and resistor jumper settings.
11-28-2019 10:07 AM
No, I am working on U280.
Probably, I need to care about pushbutton and resistor jumper settings for the PCIe reference clock as well. Thanks.
03-22-2020 10:34 PM