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paulwittib
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Registered: ‎06-22-2009

decoding BARHIT within PIO_EP.vhd of PCIe example design

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Can I decode a BARHIT signal within PIO_EP.vhd using m_axis_rx_tuser as shown below?  I use the highest bit as the register enable.  This works in simulation but does not seem to work on my SP605 eval board.  My other option would be to pull in trn_rbar_hit_n from PCIe.vhd but that was a little more painful, I thought the code below would work fine.  Any thoughts are much appreciated. 

 

 
process(clk)
  begin
    if rising_edge(clk) then
      if (m_axis_rx_tuser(21) = '1') then
       SYSCHIP_BAR_HIT <= m_axis_rx_tuser(9 downto 2);
      end if;
    end if;
end process;

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luisb
Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

Are you using x8 Gen2?  This is the only time you'll use bit 21 of m_axis_rx_tuser.  I wouldn't recommend using this signal because the there are many undefined states.  The only states that are valid are listed in table 2-13 of UG671:

http://www.xilinx.com/support/documentation/ip_documentation/ug671_V6_IntBlock_PCIe.pdf

 

Why not use m_axis_rx_tready?

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luisb
Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

Are you using x8 Gen2?  This is the only time you'll use bit 21 of m_axis_rx_tuser.  I wouldn't recommend using this signal because the there are many undefined states.  The only states that are valid are listed in table 2-13 of UG671:

http://www.xilinx.com/support/documentation/ip_documentation/ug671_V6_IntBlock_PCIe.pdf

 

Why not use m_axis_rx_tready?

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paulwittib
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Registered: ‎06-22-2009

that worked.  Thanks

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