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eiownlee
Observer
Observer
1,579 Views
Registered: ‎03-26-2018

difference between mcs and bit file,xdma pcie core

Hi,

    The developing board is a xcvu3p, and the fpga starts from two 256 Mbit QSPI flash memory device configured as an x8 SPI device (Micron part numbers MT25QU256ABA8E12-1SIT) .

    The project connects xdma pcie core with cmac usplus core to transfer data. With the bit file, the pcie device can be recognized by the host and work well. When I download the mcs file generate from the bit file, restart the host, there is the problem: the pcie device can be recognized by the host, but it can't receive data from the umac.

    The mcs is generated with the command: write_cfgmem -format MCS -interface SPIx8 -size 64 -loadbit "up 0x0 E:/bit_mcs/0512/pcie_top.bit up 0x2000000 E:/bit_mcs/0512/pcie_top.bit" -force -file E:/bit_mcs/0512/pcie_top.mcs

    The xdma pcie core and constraints are set as follows:

2018-05-12 13_01_05-project_1 - [E__pcie_ether_project_1.xpr] - Vivado 2017.2.png
2018-05-12 13_02_16-Re-customize IP.png
2018-05-12 13_18_41-Edit Device Properties.png
2018-05-12 14_33_15-Edit Device Properties.png
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7 Replies
bethe
Xilinx Employee
Xilinx Employee
1,514 Views
Registered: ‎12-10-2013

Can you please ensure that the Bitstream setting for PERSIST is not being set anywhere?

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eiownlee
Observer
Observer
1,501 Views
Registered: ‎03-26-2018

Hi,

 

    I use the default SelectMAP setting as follows, and I didn't set any other constraint

    

2018-05-22 16_20_37-Edit Device Properties.png
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venkata
Moderator
Moderator
1,474 Views
Registered: ‎02-16-2010

How do you connect the CMAC core with XDMA? If you have a block diagram to review, it can help.
When the issue is found, I hope XDMA is recognized at Gen3x16. Please confirm.
Have you added any probes to know where the data path is broken?
Whether CMAC has achieved link up when the issue is found?
Whether SPI flash has only one .bit file?
If you apply a pulse on the sys_reset input of CMAC IP, whether the design will recover?
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eiownlee
Observer
Observer
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Registered: ‎03-26-2018

Hi,

    The XDMA part is as follows, and the CMAC is connected to XDMA through the AXI_ST bridge, which is user logic.

The problem is the bit file can work,  and mcs file can be recognized as pcie device, but the data can't be transferred between

XDMA and CMAC. And  I generate only one bit file, and I connect the sys_reset to the vio IP.

    At first I thought it may be the problem of tandem setting, which loads the pcie part correctly and the rest part incorrectly. So I check the corresponding setting of tandem(PR),hope you to give some advice.

    I have two more question:

    1.    I generate bit file with the constraints"set_property HD.TANDEM_BITSTREAMS SEPARATE [current_design]", so I get two bit files: *_tandem1.bit and *_tandem2.bit. What's the command to generate the mcs?   

I use  write_cfgmem -format mcs -interface SPIx8 -size 64 -loadbit "up 0x0 *_tandem1.bit up 0x2000000 *_tandem2.bit" *.mcs 

and it doesn't work.

    2.     The *.ltx file seems not work with the mcs file, when I reboot the computer, the *.ltx file can't probe signals from the device.

 

 

 

    

 

2018-05-25 18_09_04-project_1 - [E__pcie_ether_project_1.xpr] - Vivado 2017.2.png
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bethe
Xilinx Employee
Xilinx Employee
1,420 Views
Registered: ‎12-10-2013

Can you share a screen shot of your Tandem settings from the PCIe IP? 

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eiownlee
Observer
Observer
1,397 Views
Registered: ‎03-26-2018

Hi bethe,

 

       Sure, the setting of pcie are as follows

2018-05-31 09_43_29-Re-customize IP.png
2018-05-31 09_45_00-project_1 - [E__project_pcie_ether_project_1.xpr] - Vivado 2017.2.png
2018-05-31 09_56_14-Edit Device Properties.png
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bethe
Xilinx Employee
Xilinx Employee
1,381 Views
Registered: ‎12-10-2013

Hi @eiownlee,

 

1) If you could please generate a PCIe example design with Tandem PROM and ensure you are grabbing all the necessary constraints from there.  Among others, PERSIST will need to be set.

 

2) For the correct mcs generation based on the 2 bit files, please review Product Guide 213 - Chapter 3 - Tandem PROM section

 

 

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