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Visitor
Visitor
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Registered: ‎02-25-2009

double the trn_clk

Hello,

 i want to generate a clk with the double the trn_clk frequency, ie. 125 MHz! But mapping does not allow me to add a DCM with trn_clk as input, because trn_clk is already output of a DCM somewhere in the EP.

So my approach was to generate the 125 MHz trn_clk2 via the clk_fx output of a DCM with ref_clk as input.

To get a phase relationship between trn_clk and trn_clk2 i used a

….  FROM trn_clk2 TO trn_clk 3 ns;

constraint!

 

This constraint is met after PAR, but I still get timing violations in the running design when i pass data from the trn_clk2 to the trn_clk domain (i used a FDE to guarantee stable data@trn_clk2 on a trn_clk rising edge)!

 

Is there a better way to double  the trn_clk, or even a differnent way to fifo buffer the data from trn_td with respect to DWs or QWs arriving!

 

Thanks a lot in advance,

Paul

 

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