02-17-2011 04:39 AM
Device : Virtex5 110 LXT -2
OS : Linux
Simulator : IUS
Language : Verilog
I'm verifing my design with endpoint PCIe logic.
It's simulating with dsport model.
( dsport <- pcie -> my design with endpoint PCIe)
The issued TLP from dsport is responded by the endpoint PCIe IP in my design.
The response is malformed TLP.
Why is it?
I'm attached the simulation log and .xco.
02-18-2011 11:26 AM
I would look at the trn interface on both sides (root port and endpoint) and verify that payload matches the length fied of the TLP. Also make sure to look at the trn_trem_n signal.
02-20-2011 06:25 PM
The.../endpoint_blk_plus_v1_13/simulation/dsport/pcie_2_0_rport_v6.v includes the trn_trem_n signal.
This signal is not 1bit signal but 8bit bus signals.
But the trn_trem_n signal in pcie_2_0_rport_v6.v is 1 bit signal.
Why is it?
May because of it, is malformed message issued?
02-21-2011 04:56 PM
The DSPORT uses the Root Port configuration of the Virtex-6 PCI Express core. The Virtex-6 core trn_trem_n signals is only one bit for the Virtex-6 core. You can see this in the Virtex-6 user guide:
The Virtex-5 core has the trn_trem_n signal as an 8-bit signals, however they are all connected together. For example, all 8 signals are either high or all low. You can read about this in the V-5 UG:
Perhaps you can post a picture of the packet. Please include all of the trn interface.