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Anonymous
Not applicable
5,213 Views

endpoint_blk_plus_v1_13 RTL simulation problem.

Hi,

 

Device : Virtex5 110 LXT -2

OS : Linux

Simulator : IUS

Language : Verilog

 

I'm verifing my design with endpoint PCIe logic.

It's simulating with dsport model.

( dsport <- pcie -> my design with endpoint PCIe)

 

The issued TLP from dsport is responded by the endpoint PCIe IP in my design.

The response is malformed TLP.

Why is it?

 

I'm attached the simulation log and .xco.

 

Regards

Michael

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4 Replies
luisb
Xilinx Employee
Xilinx Employee
5,197 Views
Registered: ‎04-06-2010

I would look at the trn interface on both sides (root port and endpoint) and verify that payload matches the length fied of the TLP. Also make sure to look at the trn_trem_n signal. 

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Anonymous
Not applicable
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Hi Luisb,

 

The.../endpoint_blk_plus_v1_13/simulation/dsport/pcie_2_0_rport_v6.v includes the trn_trem_n signal.

This signal is not 1bit signal but 8bit bus signals.

But the trn_trem_n signal in pcie_2_0_rport_v6.v is 1 bit signal.

Why is it?

May because of it, is malformed message issued?

 

Regards

Michael

 

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luisb
Xilinx Employee
Xilinx Employee
5,157 Views
Registered: ‎04-06-2010

The DSPORT uses the Root  Port configuration of the Virtex-6 PCI Express core.  The Virtex-6 core trn_trem_n signals is only one bit for the Virtex-6 core.  You can see this in the Virtex-6 user guide:

http://www.xilinx.com/support/documentation/user_guides/v6_pcie_ug517.pdf

 

The Virtex-5 core has the trn_trem_n signal as an 8-bit signals, however they are all connected together.  For example, all 8 signals are either high or all low. You can read about this in the V-5 UG:

http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

 

Perhaps you can post a picture of the packet.  Please include all of the trn interface.

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Anonymous
Not applicable
5,139 Views

Hi Luisb,
 
It's solved.
The v1.13 have the problem.
The relate document is Xilinx AR #34444.
The v1.14 is ok.
Thank you for giving yourself trouble.

 

Regards
Michael

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