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Visitor
Visitor
3,674 Views
Registered: ‎05-18-2010

error occurs when I simulate PCI Express in Modelsim on my own design

Hi,everyone:
   I can simulate the IP core "Endpoint Block Plus for PCI Express" which is generated by CORE Generator by "vsim -do simulate_mti.do" ,and the wave is correct. In Modelsim,vsim unisim.ppc405 can work correctly too.
   However,when I changed "board.v" by connecting "dsport" and test files to my own PCI Express design,things went wrong.
 

  In board.v,codes are as below.
  initial
  begin
    force xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_RECEIVER_DETECT_PASS0_BINARY =1'b0;
    force xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_RECEIVER_DETECT_PASS1_BINARY =1'b0;
    force xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_RECEIVER_DETECT_PASS0_BINARY =1'b0;
    force xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_RECEIVER_DETECT_PASS1_BINARY =1'b0;
  end
    defparam xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam xilinx_pci_exp_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_GTPRESET_SPEEDUP = 1;

   I changed these lines to my own design,"V5Card_blkpcie" is my top level,"part_pcie_ep" is the instance of "Endpoint Block Plus for PCI Express".
  initial
  begin
    force V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_RECEIVER_DETECT_PASS0_BINARY =1'b0;
    force V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_RECEIVER_DETECT_PASS1_BINARY =1'b0;
    force V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_RECEIVER_DETECT_PASS0_BINARY =1'b0;
    force V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_RECEIVER_DETECT_PASS1_BINARY =1'b0;
  end
    defparam V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i .SIM_GTPRESET_SPEEDUP = 1;
    defparam V5Card_blkpcie.part_pcie_ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i .SIM_GTPRESET_SPEEDUP = 1;

 

   When run "vsim -do simulate_mti.do" in modelsim,error is:
# Top level modules:
#  board
#  glbl
# vsim +notimingchecks +TESTNAME=pio_writeReadBack_test0 -L work -L secureip -L unisims_ver -L unisims_ver -L XILINXCORELIB_VER work.board glbl
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Error: ../board.v(99): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i ' in hierarchical name.
# ** Error: ../board.v(100): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i ' in hierarchical name.
# ** Error: ../board.v(101): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i ' in hierarchical name.
# ** Error: ../board.v(102): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i ' in hierarchical name.
# ** Error: ../board.v(104): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.
# ** Error: ../board.v(104): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.
# ** Error: ../board.v(105): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i ' in hierarchical name.
# ** Error: ../board.v(105): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i ' in hierarchical name.
# ** Error: ../board.v(106): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i ' in hierarchical name.
# ** Error: ../board.v(106): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i ' in hierarchical name.
# ** Error: ../board.v(107): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i ' in hierarchical name.
# ** Error: ../board.v(107): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i ' in hierarchical name.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution

   Then I comment these line 99-107 which include "\BU2/U0...",it runs,but still not correct.Everything seems stopped after "Transaction Reset Is De-asserted..."
# Running test {pio_writeReadBack_test0}......
# [                   0] : System Reset Asserted...
# [             4995000] : System Reset De-asserted...
# [             8522100] : Transaction Reset Is De-asserted...

 

What should I do? Please help.

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2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
3,641 Views
Registered: ‎08-06-2008

If you compare it with the example design simulation, it shouldn't be difficult to find where the problem might be. However, it might be worth trying with wildcard characters, replacing your top level name and the instance name, and see if it works.

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Visitor
Visitor
3,637 Views
Registered: ‎05-18-2010

Hi,

  Thank you for your reply.

  I have solved the problem.It's not the problem of top level name or instance name. I added the wrong IP core verilog file(the one just have IO declarationis in the example_design folder). Actually.in simulation,I should add the one in the top level directory which includes INST. 

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