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Contributor
Contributor
1,298 Views
Registered: ‎03-01-2018

errors in pcie 256bit demo( important!)

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Hi everyone,

I have seen a message here as follows:

 

PCIE3 Host Memory Write Request TLP Handling error 
 
I am working on the PCIE3 for Virtex7.  I have generated the PCIE3 core and the example design ‘PIO’ files using Vivado 13.4 .  I am using the example_design files for modeling the Root Complex side of the PCIE3 in my testbench.  When my endpoint application  sends a Host  Memory write request to the root complex the root complex modules receive the TLP correctly but it gets lost in the subsequent tasks and does not return with any payload data.  
 
After spending some time with the Xilinx provided root complex files (pci_exp_usrapp.v,  pci_exp_usrapp_com.v ),  I was able to get the Memory Write to work to some extent.  I found some problem in the pci_exp_usarapp_rx::TSK_BUILD_CQ_TO_PCIE_PKT task where it does not support Memory Write requests and also payload length field size error for Memory Read requests.    After correcting some issues I am still having problems with receiving the correct payload data.  I wonder if the Xilinx PCIE team  have some later versions of  pci_exp_usrapp.v (I am using version 3.0) which correctly handles Host Memory Write  and Memory Read originating from the PCIE endpoint.
 
Thanks,
Sachin
 

NOW,

I found another issue,

 in pci_exp_usrapp_rx.v(no matter v4.2/v4.4),when C_DATA_WIDTH=256, the demo is error.

0313.png

 

TSK_BUILD_CQ_TO_PCIE_PKT and TSK_READ_DATA is only for 64 bit bus, not 256bit.

 

and we can see TSK_READ_DATA_256 in pci_exp_usrapp_com.v

 

what I can't understand is that this issue exit for a long time, but no one in xilinx would correct the issue.

 

in this case, the tag of TLP packet will be 0, and when EP send MRD/MWR to RP, it will be error.

 

who can help me?

 

thanks a lot!

 

 

 

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Xilinx Employee
Xilinx Employee
1,551 Views
Registered: ‎08-02-2007

Re: errors in pcie 256bit demo( important!)

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The original Root Complex model has some limitations and the completer model is enhanced for newer devices and for wider width (512)

The write and read should both work for the task,tsk_read_data is not used only for “read”

 

there are also changes in the TSK you mentioned I have copied the example below

if(C_DATA_WIDTH==256)begin
          
             for(ii=0; ii<KEEP_WIDTH ; ii = ii +2)begin
            
               if(m_axis_cq_tkeep[ii] == 1'b1 ||m_axis_cq_tkeep[ii+1] == 1'b1 )
                   board.RP.com_usrapp.TSK_READ_DATA(m_axis_cq_tlast, `RX_LOG, {m_axis_cq_tdata[(ii+1)*32-1 -:32], m_axis_cq_tdata[(ii+2)*32-1 -:32]}, ~m_axis_cq_tkeep[ii+1]);
                  
             end           

 

we could make the same change for the older device (v7)

 

regards

Iris

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5 Replies
Moderator
Moderator
1,234 Views
Registered: ‎02-11-2014

Re: errors in pcie 256bit demo( important!)

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Hello @liuluren,

 

I suggest trying out the Vivado 2017.4 PIO Example Design to see if any of your described issues have been resolved. There have many many changes to the IP and IP Example Designs since Vivado 2013.4.

 

If you are still seeing issues, then please let us know.

 

Thanks,

Cory

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Contributor
Contributor
1,217 Views
Registered: ‎03-01-2018

Re: errors in pcie 256bit demo( important!)

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Re @Cory,

      The version what I use is Vivado 2017.4. PIO example with width 256bit is ok, for it is sample.when it turn to dma simulation, errors will be found.

      what I mean is that the issue had discovered for a long time, but no one pay  attention to it.

 

Thanks

liuluren

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Contributor
Contributor
1,166 Views
Registered: ‎03-01-2018

Re: errors in pcie 256bit demo( important!)

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Continue:

     I have wrote some task myself, and change the tlp pkt. and then it can received MWR/MRD request.

 

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Xilinx Employee
Xilinx Employee
1,552 Views
Registered: ‎08-02-2007

Re: errors in pcie 256bit demo( important!)

Jump to solution

The original Root Complex model has some limitations and the completer model is enhanced for newer devices and for wider width (512)

The write and read should both work for the task,tsk_read_data is not used only for “read”

 

there are also changes in the TSK you mentioned I have copied the example below

if(C_DATA_WIDTH==256)begin
          
             for(ii=0; ii<KEEP_WIDTH ; ii = ii +2)begin
            
               if(m_axis_cq_tkeep[ii] == 1'b1 ||m_axis_cq_tkeep[ii+1] == 1'b1 )
                   board.RP.com_usrapp.TSK_READ_DATA(m_axis_cq_tlast, `RX_LOG, {m_axis_cq_tdata[(ii+1)*32-1 -:32], m_axis_cq_tdata[(ii+2)*32-1 -:32]}, ~m_axis_cq_tkeep[ii+1]);
                  
             end           

 

we could make the same change for the older device (v7)

 

regards

Iris

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Contributor
Contributor
1,091 Views
Registered: ‎03-01-2018

Re: errors in pcie 256bit demo( important!)

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Re liy:

     thanks, I have corrected the issue. Now my system works well.

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