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jsandoval62
Visitor
Visitor
281 Views
Registered: ‎03-08-2021

example design (PCIE4 End Point Core) not running on vivado 2020.1

I opened the IP Example design and proceeded to run simulation.

 After running the simulation, I was expecting to see "user_lnk_up" signal in the waveform viewer.

But as you can see user clock does not quite wake up. It must be a very simple setting I am missing, 

but can figure it out.  Can some one chime in?

 

jose

jsandoval62_1-1615317609065.png

 

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2 Replies
deepthi
Xilinx Employee
Xilinx Employee
230 Views
Registered: ‎10-05-2020

Hi @jsandoval62 ,

Can you Run the Simulation for More time and see the signal status?

If it is Example Design with no changes it usually takes time around 200us or more depending on the device used and the configuration of the IP.

deepthi_0-1615351878836.png

If you run the simulation for more time you can see the signal will get asserted. (You can Run the simulation for more time by clicking on the option specified above in SS)

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Regards,

Deepthi.

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kurihara
Xilinx Employee
Xilinx Employee
230 Views
Registered: ‎07-26-2012

Can you try running a little more simulation? It take about 110us until link up

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