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Observer
Observer
1,248 Views
Registered: ‎10-09-2018

get problem with generating elf file for eyescan subsystem for PCIe

Hello dear experts,

 

inoder to test my pci port, i have added the entire IP eyescan subsystem(xapp1198) into my project, and connected them through DRP interface. Now i need to generate a corresponding .elf file for the project.

i have generated and specified the .hdf file in SDK, and also imported the provided software source code. But when i opened the code there is error showed in picture. But in fact i havent changed anything in source code.

Anyone knows how to solve this problem? how should i modify the code? Capture.PNG

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8 Replies
Observer
Observer
1,219 Views
Registered: ‎10-09-2018

Update:

 

i just commented out the line where the error is. now when i run "run_eyescan" in Vivado console, the result comes out is like a endless loop:

Capture1.PNG

can someone help me? im so exhausted...

 

 

best regards

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Observer
Observer
1,189 Views
Registered: ‎10-09-2018

i post the section of the code which is probably refered according to the message. and also the orianginal source file. Could you help me to locate the problem?

Capture2.PNG

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Xilinx Employee
Xilinx Employee
1,173 Views
Registered: ‎04-06-2010

Add you xparameters.h please
Observer
Observer
1,160 Views
Registered: ‎10-09-2018

@luisb

Thank you for your reply. now SDK reports no error anymore. But the result of running run_scan is still not right. the message is like:

Capture1.PNGdo you konw whats the problem?

 

best regards

haofei

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Xilinx Employee
Xilinx Employee
1,130 Views
Registered: ‎04-06-2010

Here's where I would start:

1. ensure your DRP is connected correctly.  The clocks too.  Look in the schematic view to double check.

2. ensure your addressing is correct between the IPI design and the C code.  Check both the BRAM and DRP addresses

3. start off with one lane; which I think you are.

4. ensure that the C-core matched the GT type you're using.

5. ensure your DRP clock frequency is constrained somewhere.

Observer
Observer
1,115 Views
Registered: ‎10-09-2018

thank you very much for your advise.

i just used the user_clk_out signal comes from PCIE IP, which is the AXI  interface clock, to drive the DRP Port. and nothing more constrains are applyed.

just connect user_clk_out to pcie_drp_clk , is it enough? how should i constrain it furthermore?

 

how should i check if the C-core matched the GT type?

 

best regrad

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Observer
Observer
1,046 Views
Registered: ‎10-09-2018

@luisb

thank you very much for your advise.

i just used the user_clk_out signal comes from PCIE IP, which is the AXI  interface clock, to drive the DRP Port. and nothing more constrains are applyed.

just connect user_clk_out to pcie_drp_clk , is it enough? how should i constrain it furthermore?

 

how should i check if the C-core matched the GT type?

 

best regrad

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Xilinx Employee
Xilinx Employee
982 Views
Registered: ‎04-06-2010

user_clk_out should work fine.  Make sure the reset to the subsystem you use is synchronous to user_clk_out.  I don't think the reset is your issue, but for this to work consistently, the synchronous reset is important.

Regarding the C-Code, let me know which SERDES (GTY, GTP ) and device you're using.  Then post the C code you're using.  Include the header. 

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