I am seeking the feasibility for my next design, basically what I want to do is to implemnet a pcie endpoint design on a xilinx virtex-5 fpga, and the host side is a cpu card which is a root complex, the question come with the dma engine, I know xilinx has a xapp1052 which is buas-master-dma and the dma is initiated from endpoint side, since there is a dma engine on the cpu card, my question is can I utilize this hard-core dma engine on cpu card together with bus master design?
An external DMA engine would perform reads and writes to the V5 FPGA, so for this you'd really need a high-performance slave design. As far as I know this is not implemented in any of the Xilinx example designs. I'm pretty sure those designs assume the slave functions are only used for programmed read and write by the CPU, and as such they don't accept more than one word at a time. For the Host side DMA to be effective, you'd need to accept longer packets as a slave. I don't think there's anything in the PCIe endpoint hardware that would prevent you from doing this. I just don't think you'll find it already done for you in an example design.