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how should I generate the reference CLK?

hello everybody

  Now I am using  a pci-pcie bridge(PEX8111) to connect the PCIE(based on FPGA)  and the host's pci interface. And the bridge need some  refclk+/-  input.  and the refclk+/- signals in the fpga core are also input signals. So I wonder  if I could use the fpga and the oscillator signal to generate refclk+/- .then i supply these signals to sys_clk+/-(the pcie clk in fpga core ) and  the bridge refclk+/-.  Which means the sysclk+/- will connect to 100M through the inner logic clk, without using two clk pins.



       will this design be Ok? hoping some answer.

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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-13-2007

Have you seen this: (Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?)


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Registered: ‎07-28-2010

The PCIe endpoint Ref clock is tied to the differential clock inputs for the gtp/gtx transceivers. You would have to physically send your generated clock off chip and connect it to the pcie bus ref clock. Note that the pcie bus ref clock needs to be common between all devices communicating on the pcie bus.


It is possible to clock the gtp/gtx transceivers from an internal clock but you would have to modify the pci endpoint implementation. You would still have to provide that same clock to the pcie bridge that is communicating with your endpoint.


Does the (PEX8111) not provide a reference clock signal?

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O thanks .The pex 8111 didn't supply a refclk . and it ask a refclk in.

in my design



       host ->  |  pci /pcie |  -> fpga



So the host supplies the 66Mhz  clk for  pci input and  there's no refclk supply for pex8111. So I want to supply the refclk  with fpga .

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