UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
254 Views
Registered: ‎01-24-2018

how to control pcie reset input (sys_rst_n) and xdma bridge's axi_aresetn

Jump to solution

All,

 

Because we are using Xilinx PCIE driver, so from SW point of view, how to control pcie reset input (sys_rst_n) and xdma bridge's axi_aresetn??

the FPGA is Virtex U+, by using Xilinx PCIE driver, is it possible to assert/de-assert those two reset from upper level SW? 

How to do it?

 

Thank you very much!

 

Best,

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
223 Views
Registered: ‎02-16-2010

Re: how to control pcie reset input (sys_rst_n) and xdma bridge's axi_aresetn

Jump to solution

Hi, zan_zhan@amat.com 

sys_rst_n is input to XDMA and axi_aresetn is output from the IP. 

sys_rst_n is recommended to be connected from the edge connector and controlled by the Root Port. 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
1 Reply
Moderator
Moderator
224 Views
Registered: ‎02-16-2010

Re: how to control pcie reset input (sys_rst_n) and xdma bridge's axi_aresetn

Jump to solution

Hi, zan_zhan@amat.com 

sys_rst_n is input to XDMA and axi_aresetn is output from the IP. 

sys_rst_n is recommended to be connected from the edge connector and controlled by the Root Port. 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------