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Observer
Observer
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Registered: ‎10-09-2018

how to do eye scan test on PCIe IP on K7 fpga

Dear team of Xilinx,

 

i am developing a PCIe port on a kintex 7 fpga by using example design of IP DMA/Bridge Subsystem for PCI Express v4.0 (pg195).

Now it is necessory to get a eye diagram to test the physical connection. i have looked the reference design XAPP1198, but have on idea if it fit to my case and how to get it work. Apparently it only works for evaluation boards, but i have my K7 fpga on a customerboard.

 

So my question is how to do the eye scan test for my case? please help me.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

The XAPP will work on non-demo boards.  The main thing is to have the DRP interface accessible.  If you look into the project, you should be able to see that the XAPP is primarily interfacing with the DRP interface to extract the Eye information.

Observer
Observer
752 Views
Registered: ‎10-09-2018

Hello luisb,

 

thank you for your replay. I am now working on XAPP1198. The problem now is that i just need 1 DRP port, because i have only one lane on my PCIe port so that only one transceiver need to be test, but it generates automatically 8 DRP ports. How to modify it to 1?

 

and if i build a eyescan subsystem with 1 DRP port in IP Intergrator by my self. how to execute a eyescantest with it? now it is executed by runing the command script "run_eyescan", but i cant understand it quitely. is there any other ways?

 

best regards

haofei

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