01-21-2021 02:58 PM - edited 01-21-2021 03:08 PM
I can never figure this one out with VIVADO Address editor, why can't the address editor just automatically figure of how to assign addresses and then refuses to let you change their value to something that works? I should be able to connect S_AXI_CTL and S_AXI to the same axi intercon and not have a conflict? yes? no? is there a work around? (See Below)
01-21-2021 03:05 PM
I try to reduce the address aperture to 16M instead of 1G of S_AXI_CTL to match more closely the configuration space of the PCIE core... and it gives me this error.... which makes no sense to me... why can't i reduce the address space to be smaller?
01-22-2021 09:07 AM
The work around was to:
1. create AXI INTERCON 1 for ZYNQ M AXI GP0 Interface
2. create second AXI_INTERCON 2 for ZYNQ M AXI GP1 Interface
3. Create Third AXI_INTERCON 3 for ZYNQ S AXI GP0 Interface
1. connect PCIE S_AXI ==TO==> AXI Intercon 1
2. connect PCIE S_AXI_CTL ==TO==> AXI Intercon 2
3. connect PCIE M_AXI ==TO==> AXI Intercon 3
4. make your eyes crossed connecting Clocks and Resets...