cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
xikun.dai
Explorer
Explorer
9,356 Views
Registered: ‎03-25-2014

larger max_payload_size has lower performance

Hi, we have 2 develop board with fpga device v7-690t-ffg1761,and implement a pcie gen3 x8 rp on one board, implement a pcie gen3 x8 ep on other borad, buiding the connection as below diagram use rp applicaton interface s_axis_rq_* to send data to ep, and ep receive data with application interface m_axis_cq_*, if set max_payload_size=128byte,the performance is about 36Gbps, but if we set max_payload_size=512byte, the performance is about 33Gbps,larger max_payload_size get lower performance.
0 Kudos
2 Replies
xikun.dai
Explorer
Explorer
9,338 Views
Registered: ‎03-25-2014

Hi, we have 2 development board with fpga device v7-690t-ffg1761. and implement a pcie gen3 x8 rp on one board, implement a pcie gen3 x8 ep on other borad, buiding the connection as below diagram: use rp applicaton interface s_axis_rq_* to send data to ep,and ep receive data with application interface m_axis_cq_*. if set max_payload_size=128byte,the performance is about 36Gbps, but if we set max_payload_size=512byte, the performance is about 33Gbps, larger max_payload_size get lower performance. BR Xikun
0 Kudos
kotir
Scholar
Scholar
9,328 Views
Registered: ‎02-03-2010

Hi ,

 

PCIe link bandwidth does not depend just on Max payload size.

Have a look at the below white paper.

http://www.xilinx.com/support/documentation/white_papers/wp350.pdf

 

Regards,

KR

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos