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Registered: ‎12-17-2019

memory mapped XDMA c2h from Stream FIFO

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I have the ZCU106 board.

I am using the XDMA IP connected as a memory mapped device.

Connected to the AXI4 interface i have a Streaming FIFO, receive only, 1K deep by 256 wide (32KB).

The AXI DMA address of the FIFO is 0x44a00000. And the receive addr for DMA is 0x44a01000.

I can write to the FIFO over AXI stream using the AXI lite register interface i have configured.

I can do DMA access of 4K bytes no problem. I can do multiple DMA reads of 4K no problem.

I want to increase the DMA read size.

 

What could be the problem?

We are using XDMA linux driver. 

We can read from DDR memory or various sizes just fine.

 

After looking at the descriptors it looks like the second descriptor address increments. We get erorr 512.

We then set the flag to stop the address incrementing. Still not working. We get a polling timeout now. The error is a decoder error from C2H Channel Status (0x40)

Any help would be great - Thanks in advance.

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Registered: ‎12-17-2019

Re: memory mapped XDMA c2h from Stream FIFO

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We have resolved the issue - we were not on a 4k boundary.

The driver has an io_ctl to DMA from FIFO rather than DDR however somehow setting bit 25 of the control register caused us issues. We modified the driver to not increment the descriptor and not set bit 25 of the control reg. This now works. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-09-2019

Re: memory mapped XDMA c2h from Stream FIFO

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Hi,

I would recommend looking at PG195 specifically the section about descriptors on page 24. Make sure your descriptors are aligned to 32 byte boundaries and each block of descriptors does not cross a 4K boundary.

Also, it would be helpful to see the the PCIe RC and RQ interfaces to better understand what is happening.

 

Thanks,

Matt

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Highlighted
150 Views
Registered: ‎12-17-2019

Re: memory mapped XDMA c2h from Stream FIFO

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We have resolved the issue - we were not on a 4k boundary.

The driver has an io_ctl to DMA from FIFO rather than DDR however somehow setting bit 25 of the control register caused us issues. We modified the driver to not increment the descriptor and not set bit 25 of the control reg. This now works. 

View solution in original post

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