10-22-2009 09:30 AM
I am an newbie in using PCIe. I am currently using ISE 10.1.03.
I generated a endpoint block plus core using the coregen and from the release notes
which is in the project folder I know the core version is 1.9, there is no subversin.
I know from AR#30124, the generated core should be patched in order to make it
working properly, my question is the AR#30124 has patches listed for V1.9.1/V1.9.2/V1.9.3/
V1.9.4, looks like there is no patch for V1.9, what should I do in this situation?
thanks in advance,
10-22-2009 09:35 AM
The patch brings the base v1.9 core up to the version of the patch. So if you install the v1.9.4 patch over the v1.9 core, you will then have the v1.9.4 core.
10-22-2009 09:35 AM
This AR keeps a history of all released patches.
All the v1.9 patches listed are to be applied over the v1.9 core in 10.1sp3, but they were released at different times.
If you must use v1.9, then you just need to install the v1.9.4 as its a cumultive patch.
However, I would recommend going to 11.3 v1.12 if you can.
10-22-2009 10:51 AM
thanks Kyle and John for help.
Since my tools version is 10.1SP3, is it still possible to patch the core from v1.9 upto 11.3 V1.12 without ISE 11.3 installed?
the AR#30124 has patch only upto V1.10.1, where to find 11.3 V1.12?
10-22-2009 11:21 AM
thanks for clarifying me.
BTW, I have a ML505 evaluation kit at hand, if I would like to verifying the generated PIO design on this hardware,
what do I have to do to the ucf file, the generated ucf doesnot include the TX and Rx pin location, do I have to add
them in ucf?
10-22-2009 11:32 AM
This Answer Record should have the info for ML505 (don't worry about the ES stuff):
Here is the important text from that AR:
ML505 and ML506
The ML505 and ML506 uses GTP location X0Y1 for the single lane interface. Use the "Xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1_ES.ucf" file (ML505) or "Xilinx_pci_exp_blk_plus_1_lane_ep-XC5VSX50T-FF1136-1_ES.ucf" file (ML506)from the UCF zip archive and change the GTP location to:
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_gt_wrapper_i/GTPD.GTP_i" LOC = GTP_DUAL_X0Y1 ;
The reset and clock constraint locations for this board are as follows:
NET "sys_reset_n" LOC = "AC24" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
NET "sys_clk_p" LOC = "AF4" ;
NET "sys_clk_n" LOC = "AF3" ;