UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer babu_image@
Observer
1,023 Views
Registered: ‎10-25-2017

pcie RC ---waiting for the signal

Hi Guys,

 

 In my Project, I am using PCIE example(IP) design(we are directly getting from vivado .Ultra Scale Devices Gen3 Integrated Block for PCI Express v4.4 ) . In stead of their design ,I am  using my design . the problem is--need to send the data  from pcie_core to RC model .I have awaddr ,awvalid ,wvalid &wdata these four I need to send to RC model. 

 In AXI we are sending awvalid from master to slave ,at that slave will tell I am ready to accept your address (i.e awready) ,like that what is the signal we have from RC Model 

 

Thanks in advance !!!!!!!

 

capture1.png

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
991 Views
Registered: ‎07-26-2012

Re: pcie RC ---waiting for the signal

I'm not sure if I understand your question correctly. Do you expect a reply from RP on AXI bus after you send a request from EP ( FPGA ) to RP?

 

If your request is Memory Read ( Non-Posted), RP returns a completion and PCIe core as EP puts the read data on AXI bus. However, If your request is Memory Write ( Posted), RP does not reply using a packet to EP and the user logic does not see a reply from RP. Handshaking between RP and EP is done at Data Link Layer.

 

0 Kudos
Observer babu_image@
Observer
970 Views
Registered: ‎10-25-2017

Re: pcie RC ---waiting for the signal

thanks for your reply kurihara . actually what I am doing is , I am forcing the values into PCIE core.so I am unable to see those values into EP.
In Xilinx example ,they gave sample_tests.v file , in that file totally three test cases are there .so I am using pio_write_back _test case for single read and write. now I am forcing the values at pcie core, I am unable to understand , where i need to force the values in the test case. can you please help me out.
0 Kudos
Xilinx Employee
Xilinx Employee
956 Views
Registered: ‎07-26-2012

Re: pcie RC ---waiting for the signal

If you use Xilinx example tests:  "pio_writeReadBack_test0" instead of your design and you also want to change the write data, changed the following values depending on the EP's BAR setting ( 32 or 64 Space)

 

// Event : Memory Write 32 bit TLP
//--------------------------------------------------------------------------


board.RP.tx_usrapp.DATA_STORE[0] = 8'h04;
board.RP.tx_usrapp.DATA_STORE[1] = 8'h03;
board.RP.tx_usrapp.DATA_STORE[2] = 8'h02;
board.RP.tx_usrapp.DATA_STORE[3] = 8'h01;
board.RP.tx_usrapp.DATA_STORE[4] = 8'h14;
board.RP.tx_usrapp.DATA_STORE[5] = 8'h13;
board.RP.tx_usrapp.DATA_STORE[6] = 8'h12;
board.RP.tx_usrapp.DATA_STORE[7] = 8'h11;

 

or

 

//--------------------------------------------------------------------------
// Event : Memory Write 64 bit TLP
//--------------------------------------------------------------------------


board.RP.tx_usrapp.DATA_STORE[0] = 8'h64;
board.RP.tx_usrapp.DATA_STORE[1] = 8'h63;
board.RP.tx_usrapp.DATA_STORE[2] = 8'h62;
board.RP.tx_usrapp.DATA_STORE[3] = 8'h61;
board.RP.tx_usrapp.DATA_STORE[4] = 8'h74;
board.RP.tx_usrapp.DATA_STORE[5] = 8'h73;
board.RP.tx_usrapp.DATA_STORE[6] = 8'h72;
board.RP.tx_usrapp.DATA_STORE[7] = 8'h71;

 

0 Kudos
Observer babu_image@
Observer
946 Views
Registered: ‎10-25-2017

Re: pcie RC ---waiting for the signal

thanks kurihara for continuous replies

I need to force the values on pcie core.

  pcie core having master and slave. I am forcing the values at master side.

  force  m_axis_awaddr = 32'habcd;

  force  m_axis_awvalid = 1;

  force m_axis_wvalid =1;

  force m_axis_wdata = 32'h abcd_abcd;

the above traffic i need to see in the root complex signals.

where I need to put the above code in the test case file (sample_test.v file).

0 Kudos
Moderator
Moderator
904 Views
Registered: ‎02-16-2010

Re: pcie RC ---waiting for the signal

To send the packet to RP, you will need to drive S_AXI port of the Bridge.

Check xilinx_axi_pcie4_ep.v file. You can find access to both m_axi_* and s_axi_* ports .
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos