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r5h1n
Observer
Observer
4,596 Views
Registered: ‎08-19-2010

pcie endpoint block plus v1_14

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Hello .

when i generate the core of pcie "endpoint block plus v1_14"  it gives following warning messages: 


 

WARNING:sim:215 - This core does not support ASY symbol generation.
WARNING:sim:93 - NGC output will not be generated for this core.

 


I got instantaition tempalate, but when i synthesise the design in ISE 12.2 it give two error messages; 

 

 

ERROR:HDLCompilers:27 - "ipcore_dir/ppp/example_design/dual_core/xilinx_pci_exp_secondary_ep.v" line 57 Illegal redeclaration of 'xilinx_pci_exp_secondary_ep'


ERROR:HDLCompilers:27 - "ipcore_dir/ppp/example_design/pci_exp_1_lane_64b_ep.v" line 56 Illegal redeclaration of 'ppp'

 

I just simply instantiated the design and define the input and output and then synthesised it and got these errors . 

completely stuck in the begining...

 

regards,

r5h1n

 

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luisb
Xilinx Employee
Xilinx Employee
5,517 Views
Registered: ‎04-06-2010

Did you add all of the RTL in the "example_design" and "source" directories?  Or did you just add the XCO into the project?

 

I would recommend to add all of the files that are listed in the .xst file in the "implement" directory.  I wouldn't include any more than the files that are listed in that file.  This should allow you to implement the example design within ISE.

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luisb
Xilinx Employee
Xilinx Employee
5,518 Views
Registered: ‎04-06-2010

Did you add all of the RTL in the "example_design" and "source" directories?  Or did you just add the XCO into the project?

 

I would recommend to add all of the files that are listed in the .xst file in the "implement" directory.  I wouldn't include any more than the files that are listed in that file.  This should allow you to implement the example design within ISE.

View solution in original post

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r5h1n
Observer
Observer
4,577 Views
Registered: ‎08-19-2010

I just added xco into my project. now i added the example design.

thanks it synthesises successfully.

 

If I want to add my own logic to tx and rx my own required data then where should add it ?? 

 

regards,

r5h1n

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r5h1n
Observer
Observer
4,560 Views
Registered: ‎08-19-2010

I just added xco into my project. now i added the example design.

thanks it synthesises successfully.

 

If I want to add my own logic to tx and rx my own required data then where should add it ?? 

 

regards,

r5h1n

0 Kudos