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2,916 Views
Registered: ‎04-06-2018

pcie example design

hi,

i am using Artix ac701 development board for PCIe 7 series integrated block example design. based on example design it is possible to transfer 1DW of data payload per transaction, i would like to know whether we can increase the no: of data payload?. also in this design first 3DW header appear first then a DW of data payload, is it possible to get a single header+ continous data?

how i/o transactions happen in this example design?

 

regards,

Shekha Shoukath

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8 Replies
borisq
Xilinx Employee
Xilinx Employee
2,869 Views
Registered: ‎08-07-2007

hi shekhashoukath@gmail.com

 

PIO example design can only support single DW transactions.

Pls refer to pg054 page 270

 

"Supports single DWORD payload Read and Write PCI Express transactions to 32-/64-bit
address memory spaces and I/O space with support for completion transaction layer
packets (TLPs)"

 

You can generate example design by the XDMA IP instead of the base intergrated block IP, and use AR65444 driver as host.

https://www.xilinx.com/support/answers/65444.html

So that you can transter multiple DWs at a time.

 

Thanks,

Boris

 

 

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2,828 Views
Registered: ‎04-06-2018

hai,

thanks for the reply. we can change the read length in tx engine, suppose using some tool the length field in the first DW was changed to more than one, now my question wiil it accept more than one DW of data payload ?

 

 

 

regards,

Shekha Shoukath

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liy
Xilinx Employee
Xilinx Employee
2,826 Views
Registered: ‎08-02-2007

The limitation is only with the example code

the IP core support length up to MPS (128,256 byte or 512 byte or 1024 byte ) of write command

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2,797 Views
Registered: ‎04-06-2018

hi ,

Thanks for reply.

xdma ip is not available in ip catalogue for pcie .

does xc7a15tfgg484 or xc7a200tfbg676 support xdma ip?

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liy
Xilinx Employee
Xilinx Employee
2,793 Views
Registered: ‎08-02-2007

Yes it is supported

please select “DMA/Bridge subsystem for PCI Express”

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2,753 Views
Registered: ‎04-06-2018

hai ,

thanks for reply. i have attached the screenshot for selecting pcie ip, you can see that list does't contain xdma ip.

 

 

 

 

regards,

Shekha Shoukath

xdma_ip.png
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2,747 Views
Registered: ‎04-06-2018

hai,

i am using Artix 7 series FPGA(xc200tfbg676-2) for developing a PCIe interface. i need to view the read and write operation so i probed those signals to an ila core whose clk freq is 200MHz(this clock is obtained from from differential to single ended utility buffer) , now  i need to invert the clk freq to ila so i added a utility vector logic for NOT operation , and connected that inverted output as clk to another ila. but when i run immediate trigger it shows" Unable to arm ila2, the core clk is slow/ no core clk coonected to this ila/ ila core may not meet timing ". Actually there is no timing violation . Also in another case i used fifo generator ip, i have connected pcie's system reset(asynchronous ,active low) to fifo reset . when i build its shows the following error:

 

 

 

sys_rst_fifo.png
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venkata
Moderator
Moderator
2,610 Views
Registered: ‎02-16-2010

It seems you are instantiating fifo_gen module outside the PCIe IP example.

PCIe IP example instantiates a IBUF primitive at the top file and connects the output of the IBUF instance to the IP.
IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));

You could move the IBUF instance from PCIe IP example to the file in which PCIe IP example and fifo gen module exists. connect the output of IBUF instance to both PCIe IP example and fifo gen.
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