07-16-2018 01:34 AM
i am using Artix ac701 development board for PCIe 7 series integrated block example design. based on example design it is possible to transfer 1DW of data payload per transaction, i would like to know whether we can increase the no: of data payload?. also in this design first 3DW header appear first then a DW of data payload, is it possible to get a single header+ continous data?
how i/o transactions happen in this example design?
07-16-2018 11:17 PM
PIO example design can only support single DW transactions.
Pls refer to pg054 page 270
"Supports single DWORD payload Read and Write PCI Express transactions to 32-/64-bit
address memory spaces and I/O space with support for completion transaction layer
You can generate example design by the XDMA IP instead of the base intergrated block IP, and use AR65444 driver as host.
So that you can transter multiple DWs at a time.
07-19-2018 10:52 PM
thanks for the reply. we can change the read length in tx engine, suppose using some tool the length field in the first DW was changed to more than one, now my question wiil it accept more than one DW of data payload ?
07-19-2018 10:56 PM
The limitation is only with the example code
the IP core support length up to MPS (128,256 byte or 512 byte or 1024 byte ) of write command
07-22-2018 11:12 PM
Yes it is supported
please select “DMA/Bridge subsystem for PCI Express”
07-27-2018 01:28 AM
thanks for reply. i have attached the screenshot for selecting pcie ip, you can see that list does't contain xdma ip.
07-27-2018 02:00 AM
i am using Artix 7 series FPGA(xc200tfbg676-2) for developing a PCIe interface. i need to view the read and write operation so i probed those signals to an ila core whose clk freq is 200MHz(this clock is obtained from from differential to single ended utility buffer) , now i need to invert the clk freq to ila so i added a utility vector logic for NOT operation , and connected that inverted output as clk to another ila. but when i run immediate trigger it shows" Unable to arm ila2, the core clk is slow/ no core clk coonected to this ila/ ila core may not meet timing ". Actually there is no timing violation . Also in another case i used fifo generator ip, i have connected pcie's system reset(asynchronous ,active low) to fifo reset . when i build its shows the following error:
08-22-2018 10:53 AM