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rasith
Visitor
Visitor
8,502 Views
Registered: ‎05-16-2014

pcie lane

Hi,

 

    In pcie x8 lane,

    lane 0 and lane 7 was not working what is behavior of PCIE root complax ?

 

Regards,

rasith

 

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3 Replies
kotir
Scholar
Scholar
8,496 Views
Registered: ‎02-03-2010

Hi,

 

If lane zero is not working , then link will not be up.

 

If lane7 alone not working , then the link will train down to x4 instead of x8(targetted)

 

Regards,

KR

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rasith
Visitor
Visitor
8,488 Views
Registered: ‎05-16-2014

Hi,


  In x8 PCIE lane without lane reversal,


1: lane 0,lane 2,lane 7 is not working then root complex train the link as x4 used
i.e., lane 1,3,4,5 act as lane0,1,2,3 .Is it correct?

2: lane 3 is not working then root complex train the link as x4 used
i.e.,lane 4,5,6,7 act as lane 0,1,2,3. Is it correct?

3: lane 3 is not working then root complex train the link as x2 used
i.e.,lane 0,1 act as lane 0,1, and all other lanes are inactive. Is it correct?

 

Regards,

rasith

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kotir
Scholar
Scholar
8,481 Views
Registered: ‎02-03-2010

Hi ,

 

It does not work that way.

 

Have a look at the Base specification section 4.2.2 (Framing and Application of Symbols to Lanes).

 

It says as below.

 

For Links wider than x1, the STP Symbol (representing the start of a TLP) must be placed in
Lane 0 when starting Transmission of a TLP from a Logical Idle Link condition.

 

For Links wider than x1, the SDP Symbol (representing the start of a DLLP) must be placed in
Lane 0 when starting Transmission of a DLLP from a Logical Idle Link condition.

 

If lane zero does not work , the is no link up.

 

Regards,

Koti Reddy

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