UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer kjb
Observer
1,275 Views
Registered: ‎12-03-2013

pcie on xc6vlx130t not translating

Jump to solution

Hello,

 

I am currently trying to implement a Xillybus PCIe core on a Virtex-6 xc6vlx130t

 

As per the instructions on the Xillybus webpage I copied over the constraints from the example design and modified the LOC constraints according to my manufacturer's reference. I should add, that I have gone through this procedure a few times for Spartan-6 devices and it worked every time.

 

However this time I end up having problems translating the design. I receive the  following error:

ERROR:NgdBuild:604 - logical block
   'xillybus_ins/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANALIGN_FI
   X_3752' with type 'GTX_DRP_CHANALIGN_FIX_3752_V6' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, case
   mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'GTX_DRP_CHANALIGN_FIX_3752_V6' is not
   supported in target 'virtex6'.

ERROR:NgdBuild:604 - logical block
   'xillybus_ins/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANALIGN_FI
   X_3752' with type 'GTX_DRP_CHANALIGN_FIX_3752_V6' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, case
   mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'GTX_DRP_CHANALIGN_FIX_3752_V6' is not
   supported in target 'virtex6'.

ERROR:NgdBuild:604 - logical block
   'xillybus_ins/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANALIGN_FI
   X_3752' with type 'GTX_DRP_CHANALIGN_FIX_3752_V6' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, case
   mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'GTX_DRP_CHANALIGN_FIX_3752_V6' is not
   supported in target 'virtex6'.

ERROR:NgdBuild:604 - logical block
   'xillybus_ins/pcie/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANALIGN_FI
   X_3752' with type 'GTX_DRP_CHANALIGN_FIX_3752_V6' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, case
   mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'GTX_DRP_CHANALIGN_FIX_3752_V6' is not
   supported in target 'virtex6'

 

As you can see the problem is actually inside the Xilinx PCIe core itself, and has nothing to do with the Xillybus code. Regenerating the core to ensure it is for the current architecture had no effect.

 

Upgrading the core to the newest version (the Xillybus pcie core is v1.7) is not an option, since the 2.5 version uses an AXI interface. Anyway the 1.7 version is not deprecated, so should work.

 

I then thought that I might have a problem with copying the XCO core from the example design and generated the core from scratch using coregen, simply setting the settings identical to the ones in the Xillybus example. Again to no effect.

 

I presume there is a problem inside the PCIe core connected to the part number I use, since the ML605 version worked for me in the past.

 

Has someone encountered this problem before and solved it?

 

Thanks in advance for any help.

 

Best regards

0 Kudos
1 Solution

Accepted Solutions
Observer kjb
Observer
1,973 Views
Registered: ‎12-03-2013

Re: pcie on xc6vlx130t not translating

Jump to solution

Hi there,

 

So the problem stemmed from the XCO file not having the correct file list it appears.

 

Instead of adding the XCO file to the project, the solution was to add all generated VHDL files manually.

 

Hopefully this helps someone in the future.

0 Kudos
1 Reply
Observer kjb
Observer
1,974 Views
Registered: ‎12-03-2013

Re: pcie on xc6vlx130t not translating

Jump to solution

Hi there,

 

So the problem stemmed from the XCO file not having the correct file list it appears.

 

Instead of adding the XCO file to the project, the solution was to add all generated VHDL files manually.

 

Hopefully this helps someone in the future.

0 Kudos