cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Surya_ks
Observer
Observer
348 Views
Registered: ‎12-22-2020

pcie to QSFP

Hello 

I am trying to do transmit data from PCIe to qsfp  ,  attached my design in the post .. while  validating the design there is no error but showing critical warning after implementation about the clocks in the design . can you check anyone in the design give below .

Thank you

design.PNG
0 Kudos
3 Replies
pvenugo
Moderator
Moderator
263 Views
Registered: ‎07-31-2012

@Surya_ks ,

Please share the clock warnings details which you are encountering.

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Surya_ks
Observer
Observer
195 Views
Registered: ‎12-22-2020

Hello 

I share the critical warning and the error getting while generating the bit-stream . Anyone please help me to solve the  problem in the design 

Thank you.

critical.PNG
error.PNG
0 Kudos
nmanitri
Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎06-13-2018

Hi @Surya_ks ,

 

In your reference design, I am not seeing a clock with name sys_clk. Could you please correct the clock name in your xdc file. Please replace sys_clk with diff_clock_rtl_0 and see still error persist?

Regards,

Naveen 

0 Kudos