problem of simulating pcie core 1.6. please help

[zj377]

Hi,

I'm using ISE 10.1 vertex5 and Modelsim SE 6.4a and the pcie endpoint block plus core v1.6.
in the file named function,there is a script. Is it only used in ise ?can it be used in modelsim?
I have tried to use it in modelsim,but there is error,

 # vsim -L secureip -L UNISIMS_VER work.board work.glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(83): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/pcie_ep ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(83): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/pcie_ep ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(86): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(86): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.

I comment out the two lines contain "\BU2/U0/pcie_ep0/pcie_blk/pcie_ep " and "\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i",
and sinulate again,but trn_lnk_up does not assert and it's forever stuck at :

# Running test {sample_smoke_test0}......
# [                   0] : System Reset Asserted...
# [             4995000] : System Reset De-asserted...
# [             5346100] : Transaction Reset Is De-asserted...

for a long long time......

And I also have tried to simulate without using the script.I sinulate it in normal format ,but there is also problem ,
 
 # vsim -L secureip -L UNISIMS_VER work.board work.glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(83): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/pcie_ep ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(83): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/pcie_ep ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(86): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/board.v(86): Failed to find '\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i ' in hierarchical name.

I comment out the two lines contain "\BU2/U0/pcie_ep0/pcie_blk/pcie_ep " and "\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i",and sinulate again,but there happen a new error:

# ** Error: E:/item/macro_xilinx/PCIe/sim/code/PIO.v(174): (vopt-2135) Too many port connections. Expected 20, found 22.
# ** Error: E:/item/macro_xilinx/PCIe/sim/code/pci_exp_64b_app.v(292): (vopt-2135) Too many port connections. Expected 21, found 23.

please help! thank you !!

[evgenis1]

There is a "simulate_mti.do" script for ModelSim in /simulation/functional/ folder (this is what you're running, right ?) .

You can run it from ModelSim commad line as "ModelSim> do simulate_mti.do". It used to work for me.

Also, do you have to use 1.6 core. There is a newer 1.9 with lots of fixes, including simulation ones.

OutputLogic 

[zj377]

hi,

thank you for your rely.do you mean it might be the problem of the version of pcie core i used?

the version of my ise is 10.1,and the pcie version is 1.6. i need to update my ise to get the 1.9 core. i have to try the method, thank you for your remind. 

[zj377]

hi,
I am simulating pcie core 1.9 based on windows. but the core is based on linux.so there are files
named xilinx_lib_vcs.f and xilinx_lib_vnc.f pointed to $XILINX/smartmodel/lin/wrappers/
what can i do to change it to work on windows ? should i change one to point to $XILINX/smartmodel/nt/wrappers/  and delete
another one ? should i  modify other things ?
for help ! thanks!

[evgenis1]

Why don't you try an regenerate the core for WIndows. Also, xilinx_lib_vcs.f indicates that it's for VCS simulator. You're using ModelSim, right ?

[zj377]

hi,
thank you for your reply.
i use modelsim to simulate pcie core1.9. i have vsim the unisim.ppc405 without error,but the simulation
can't link up .it's strange ,i have uploaded the transcript of "vsim unisim.ppc405" and the
transcript of "do simulate_mti.do" .can you give me some advise,thank you so much!!

[evgenis1]

It takes about 80us till the PCIe link is up.

Where did you upload "do simulate_mti.do"  ?

OutputLogic 

[zj377]

i'm sorry ,here it is.

[zj377]

and it's the transcript of "vsim unisim.ppc405"

[xuefeixuan]

Hi,

I have exactly the same problem as you.Have you solved it ,and HOW?

Please help,waiting for reply.