cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
11,083 Views
Registered: ‎01-02-2010

problems with xapp1052 and ISE 11.4?

I downloaded the latest zip file for xapp 1052 today and tried to get a four lane PCI Express Gen 2 Endpoint working on an ML605 board but when I run the perl script mentioned in the xapp I get the following error:

Elaborating module <gtx_wrapper_v6(NO_OF_LANES=6'b0100,REF_CLK_FREQ=2,PL_FAST_TRAIN="FALSE")>.
ERROR:HDLCompiler:559 - "../../../source/gtx_wrapper_v6.v" Line 275: Could not find module/primitive <GTX_DRP_CHANALIGN_FIX_3752_V6>.
Module gtx_wrapper_v6 remains a blackbox, due to errors in its contents 

I saw in another thread ("Is xapp1052 missing a file?") that jayer mentioned that this has been tested with ISE 11.3.  Has anyone else been able to get this working with ISE 11.4? 

 

Thanks,

 

Rod

0 Kudos
7 Replies
Highlighted
Newbie
Newbie
10,938 Views
Registered: ‎01-30-2010

Hallo,

 

I have also problems when implementing this 1052 with ISE11.4 and ML555. I dont know if there are the scripts included or the coregenerator 11.3.

Folloing files are missing when I create the core:

 

pcie_blk_cf_int.v

use_pll.v

xilinx_pci_exp_ep.v (it is a vhd instead)

 

Thanks and rds.,

SF 

0 Kudos
Highlighted
Newbie
Newbie
10,590 Views
Registered: ‎04-16-2010

I also meet this problem, should i change my ise version to 11.3?
0 Kudos
Highlighted
Visitor
Visitor
10,516 Views
Registered: ‎04-25-2010

Have the same problem.   This is so unacceptable!   I added

`include "../../../source/gtx_drp_chanalign_fix_3752_v6.v"
to

xst/xilinx_pci_exp_v6_ep_inc.xst 

and got the synthesis to run.  There was 2 slight timing violations after P&R.  I have not tried it in FPGA yet, so don't know if this will work.  Anybody got this to work?

 

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,505 Views
Registered: ‎09-02-2009

Hi all,

 

The 11.4 version of the V6 design added a new required file.  Because the XAPP has not been refreshed, it is missing a file.

 

To fix this issue, simply add the missing file to the '.xst' file in the directory dma_performance/fpga/implement/xst.  All of the required files for V6 are located in <core_name>/source.

 

 This will be fixed when the XAPP files are refreshed.

 

Jason

0 Kudos
Highlighted
Visitor
Visitor
8,921 Views
Registered: ‎11-10-2011

The same problem still exists in the 13.3 release (AXI PCIe IP core)

 

The possible workaround is to manually open ip_cores/pcie_ctrl.xise project in the ISE than add sources/axi*.vhd and sourecs/gtx_drp_chanalign_fix_3572.vhd files to it. Than try to recompile top design, it should be ok now.

 

My design with PCIe was succesfully implemented down to the bitfile, but it's to late to try it in the hardware, so i'll verify it tomorow.

--
WBR, Valentin
JSC "NII STT", Smolensk, Russia
Mob: +79107824811
0 Kudos
Highlighted
Visitor
Visitor
8,911 Views
Registered: ‎11-10-2011

I had to dance a magic voodoo dance, but it works now!

4-lane PCIe Gen2 on a Virtex-6 75t chip.

--
WBR, Valentin
JSC "NII STT", Smolensk, Russia
Mob: +79107824811
0 Kudos
Highlighted
Newbie
Newbie
8,792 Views
Registered: ‎03-23-2012

I was having the same problem: ISE fails during implement saying "type 'GTX_DRP_CHANALIGN_FIX_3752_V6' could not be resolved".  Adding sourecs/gtx_drp_chanalign_fix_3572.vhd to the project fixed the problem.  Many thanks for the info.

 

James

0 Kudos