01-06-2021 12:47 PM
The following signal within the xdma core has been causing issues with the PCIe device showing up in our builds:
We are using the XDMA core v4.1 and it seems that the store_ltssm which seems to be internal to the core is listed as "MARK_DEBUG" because signal shows up in ILA when we build with the ILA core.
We have had issues with the PCIE device showing when this signal is present in the ILA. We have tested this by running several builds without the signal and the PCIE device shows up without any issues. We can remove the signal post synthesis by adding the following line to our constraints file:
set_property mark_debug false [get_nets "xdma_0/inst/pcie4_ip_i/inst/store_ltssm"]
Our design passes timing when the ILA is not included but adding the ILA causes our design to fail timing closure so that can also be related to this specific problem.
Finally, we are targetting a Zynq Ultrascale+ RFSOC FPGA and the problem has been seen on multiple different boards.
My question is:
Why is the signal marked for debug by default in the first place and is there a setting on the xdma_0 IP that would allow us to remove it as opposed to removing it post synthesis.
02-15-2021 05:19 AM
Starting 2020.1, we have added the following option in the IP configuration GUI to disable store_ltssm if not required. Could you please check if that helps?
02-18-2021 05:25 AM
This is exactly what we will need. The workaround of removing the signal post synthesis worked but I was looking for a way to remove it within the core. We are on 2019.2 and plan to upgrade to 2020.2 so once we upgrade I can test this out.